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US 6,188,603 B1Granted
Nonvolatile memory device
AssigneeNEC Corporation
InventorMasaki Takeda
Life of this patent
Estimating the term…
Abstract
A nonvolatile semiconductor memory device includes a memory cell array and a check memory cell array. Each check memory cell is connected to a cell block including a plurality of memory cells and has about the same characteristic as the memory cell. A predetermined value is written to the check memory cell each time data is written to the corresponding cell block. By comparing a value stored in the check memory element to the predetermined value, the deterioration state of the memory cells is detected.
Claims10
A nonvolatile memory device comprising:
- a first nonvolatile memory element that is electrically writable;
- a second nonvolatile memory element that is electrically writable and has about the same characteristic as the first nonvolatile memory element;
- a memory controller for controlling a write/read operation of the second nonvolatile memory element such that a predetermined value is written to the second nonvolatile memory element each time a write operation is performed in the first nonvolatile memory element;
- and
- a comparator for comparing a value stored in the second nonvolatile memory element to the predetermined value,
- wherein data is written to the first nonvolatile memory element by a first write operation and the predetermined value is written to the second nonvolatile memory element by a second write operation, wherein the first and second write operations include an erase phase and a write phase which are sequentially placed within a predetermined time period,
- wherein a time period of the write phase of the second write operation is shorter than that of the first write operation.
4 more elements
A nonvolatile memory device comprising:
- a first nonvolatile memory element that is electrically writable;
- a second nonvolatile memory element that is electrically writable and has about the same characteristic as the first nonvolatile memory element;
- a memory controller for controlling a write/read operation of the second nonvolatile memory element such that a predetermined value is written to the second nonvolatile memory element each time a write operation is performed in the first nonvolatile memory element;
- and
- a comparator for comparing a value stored in the second nonvolatile memory element to the predetermined value,
- wherein data is written to the first nonvolatile memory element by a first write operation and the predetermined value is written to the second nonvolatile memory element by a second write operation, wherein the first and second write operations include an erase phase and a write phase which are sequentially placed within a predetermined time period,
- wherein a time period of the write phase of the second write operation is as long as that of the first write operation.
4 more elements
A nonvolatile memory device comprising:
- a first memory cell array including a predetermined number of cell blocks each including a plurality of first nonvolatile memory cells each being electrically writable;
- a second memory cell array including the predetermined number of second nonvolatile memory cells each of which is electrically writable and has about the same characteristic as the first nonvolatile memory cell, wherein the second nonvolatile memory cells correspond to the cell blocks, respectively;
- a first memory controller for controlling a write/read operation of a designated cell block of the first memory cell array;
- a second memory controller for controlling a write/read operation of a second nonvolatile memory cell corresponding to the designated cell block such that a predetermined value is written to the second nonvolatile memory cell each time a write operation is performed in the designated cell block;
- and
- a comparator for comparing a value stored in the second nonvolatile memory cell to the predetermined value,
- wherein the first memory controller controls such that data is written to the designated cell block by a first write operation, and the second memory controller controls such that the predetermined value is written to the second nonvolatile memory cell by a second write operation,
- wherein the first and second write operations include an erase phase and a write phase which are sequentially placed within a predetermined time period, and
- wherein a time period of the write phase of the second write operation is shorter than that of the first write operation.
6 more elements
A nonvolatile memory device comprising:
- a first memory cell array including a predetermined number of cell blocks each including a plurality of first nonvolatile memory cells each being electrically writable;
- a second memory cell array including the predetermined number of second nonvolatile memory cells each of which is electrically writable and has about the same characteristic as the first nonvolatile memory cell, wherein the second nonvolatile memory cells correspond to the cell blocks, respectively;
- a first memory controller for controlling a write/read operation of a designated cell block of the first memory cell array;
- a second memory controller for controlling a write/read operation of a second nonvolatile memory cell corresponding to the designated cell block such that a predetermined value is written to the second nonvolatile memory cell each time a write operation is performed in the designated cell block;
- and
- a comparator for comparing a value stored in the second nonvolatile memory cell to the predetermined value,
- wherein the first memory controller controls such that data is written to the designated cell block by a first write operation, and the second memory controller controls such that the predetermined value is written to the second nonvolatile memory cell by a second write operation,
- wherein the first and second write operations include an erase phase and a write phase which are sequentially placed within a predetermined time period, and
- wherein a time period of the write phase of the second write operation is as long as that of the first write operation.
6 more elements
A nonvolatile memory device comprising:
- a first memory cell array including a predetermined number of cell blocks each including a plurality of first nonvolatile memory cells each being electrically writable;
- a second memory cell array including the predetermined number of second nonvolatile memory cells each of which is electrically writable and has about the same characteristic as the first nonvolatile memory cell, wherein the second nonvolatile memory cells correspond to the cell blocks, respectively;
- a first memory controller for controlling a write/read operation of a designated cell block of the first memory cell array;
- a second memory controller for controlling a write/read operation of a second nonvolatile memory cell corresponding to the designated cell block such that a predetermined value is written to the second nonvolatile memory cell each time a write operation is performed in the designated cell block;
- a comparator for comparing a value stored in the second nonvolatile memory cell to the predetermined value;
- a third memory controller performing the write operation of the second memory cell array a predetermined number of times before the write operation is performed in the first memory cell array;
- and
- a switch for electrically separating the second memory cell array from the first memory cell array under control of the third memory controller when the write operation of the second memory cell array is performed a predetermined number of times before the write operation is performed in the first memory cell array.
5 more elements
A method for detecting a deterioration state of a first nonvolatile memory element that is electrically writable, comprising:
- performing a write/read operation of a second nonvolatile memory element that is electrically writable and has about the same characteristic as the first nonvolatile memory element such that a predetermined value is written to the second nonvolatile memory element each time a write operation is performed in the first nonvolatile memory element;
- determining whether a value stored in the second nonvolatile memory element coincides with the predetermined value;
- and
- detecting the deterioration state of the first nonvolatile memory element when the value stored in the second nonvolatile memory element does not coincide with the predetermined value,
- wherein data is written to the first nonvolatile memory element by a first write operation and the predetermined value is written to the second nonvolatile memory element by a second write operation, wherein the first and second write operations include an erase phase and a write phase which are sequentially placed within a predetermined time period, and
- wherein the time period of the write phase of the second write operation is shorter than that of the first write operation.
3 more elements
A method for detecting a deterioration state of a first nonvolatile memory clement that is electrically writable, comprising:
- performing a write/read operation of a second nonvolatile memory element that is electrically writable and has about the same characteristic as the first nonvolatile memory element such that a predetermined value is written to the second nonvolatile memory element each time a write operation is performed in the first nonvolatile memory element;
- determining whether a value stored in the second nonvolatile memory element coincides with the predetermined value;
- and
- detecting the deterioration state of the first nonvolatile memory element when the value stored in the second nonvolatile memory element does not coincide with the predetermined value,
- wherein data is written to the first nonvolatile memory element by a first write operation and the predetermined value is written to the second nonvolatile memory element by a second write operation, wherein the first and second write operations include an erase phase and a write phase which are sequentially placed within a predetermined time period, and
- wherein a time period of the write phase of the second write operation is as long as that of the first write operation.
3 more elements
Dependencies are inferred from the claim text.