Ferroelectric memory device having single bit line coupled to at least one memory cell

Abstract

A semiconductor memory device, includes: a single bit line; at least one memory cell coupled to said single bit line for storing a first charge corresponding to predetermined data; a reference voltage generation circuit for generating a reference voltage as a first voltage; a charge pump circuit for generating a second charge substantially corresponding to the reference voltage; a transistor for combining the first charge with the second charge at a read operation, thereby generating a second voltage; and a sense amplifier coupled to said single bit line for sensing and amplifying a difference between the first voltage and the second voltage, to thereby read out the predetermined data. The semiconductor memory device can reduce its chip size by employing the single bit line coupled to at least one memory cell and effectively sense and amplify the difference between the first voltage from the reference voltage generation circuit and the second voltage from the single bit line at the read operation.

Dependencies are inferred from the claim text.