Circuit for driving nonvolatile ferroelectric memory
AssigneeHyundai Electronics Industries Co., Ltd.
InventorHee Bok Kang
Life of this patent
Estimating the term…
Abstract
A nonvolatile ferroelectric memory has a plurality of bitlines, a plurality of wordlines and plate lines formed in a direction crossing the bitlines, and a reference bitline on one side of the plurality of bitlines. A cell array has a plural repetition of the plurality of bitlines and the reference bitline on one side thereof, a sense amplifier array having a plurality of sense amplifiers for sensing data on the bitlines and the reference bitlines in the cell array, a wordline and plateline driver for selective application of driving signals to the wordlines and the platelines, and a switching unit for selective turning on/off of the bitlines, the reference bitlines, and the input/output nodes on the sense amplifier array, whereby improving chip operation performance and lifetime of the chip.
Claims12
A ferroelectric memory having a plurality of bitlines, a plurality of wordlines and plate lines formed in a direction crossing the bitlines, and a reference bitline on one side of the plurality of bitlines, the ferroelectric memory comprising:
- a main cell array having a plurality of main cells, each main cell being coupled to corresponding wordline, plateline and bitline;
- a reference cell array having a plurality of reference cells, each reference cell being coupled to corresponding wordline, plateline and reference bitline;
- a sense amplifier array having a plurality of sense amplifiers for sensing data on each bitline and each reference bitline;
- a driver for providing driving signals to the wordlines and the platelines;
- a switching unit for selective connection of the bitlines and the reference bitline to input/output nodes and reference nodes, respectively, on the sense amplifier array;
- and
- a pull-up transistor for pulling-up a level of the reference bitline to a level of a supply voltage.
A nonvolatile ferroelectric memory, comprising:
- a first main cell block having a plurality of bitlines, a plurality of wordlines and platelines formed in a direction crossing the bitlines, and a main cell at a corresponding crossing point of the bitlines with the wordlines and the platelines;
- a first reference cell block on one side of the first main cell block, the first reference cell block having a reference bitline formed in a direction crossing the wordlines and the platelines and a reference cell on a corresponding crossing point of the reference bitline with the wordlines and the platelines;
- a first sense amplifier block having a plurality of sense amplifiers each sense amplifier having a bitline input/output node connected to a corresponding bitline for sensing a data on the corresponding bitline and a reference bitline input/output node connected to the reference bitline for sensing a data on the reference bitline;
- a first switching unit for selective connection of the bitline to the bitline input/output node on each of the sense amplifiers in response to a first control signal;
- a second switching unit for selective connection of the reference bitline to the reference input/output node on each of the sense amplifiers in response to a second control signal;
- and
- a pull-up transistor for pulling-up a level of the reference bitline to a level of a power supply voltage in response to a third control signal.
A nonvolatile ferroelectric memory comprising:
- a first main cell block having a plurality of bitlines, a plurality of wordlines and platelines formed in a direction crossing the bitlines, and a main cell at every second crossing point of the bitlines with the wordlines and the platelines;
- a first reference cell block on one side of the first main cell block, the first reference cell block having first and second reference bitlines formed in a direction crossing the wordlines and the platelines and a reference cell at every second crossing point of the first and second reference bitlines with the wordlines and the platelines;
- a first sense amplifier block having a plurality of sense amplifiers, each sense amplifier having a bitline input/output node connected to one of the bitlines in the first main cell block and an odd numbered reference bitline input/output node connected to the first reference bitline and an even numbered reference bitline input/output node connected to the second reference bitline;
- a first switching unit for selective connection of the bitlines to the bitline input/output nodes on the sense amplifiers;
- a second switching unit for selective connection of the first and second reference bitlines to the corresponding even and odd reference bitline input/output nodes on the sense amplifiers;
- and
- pull-up transistors for pulling-up levels of the first and second reference bitlines to a level of a power supply voltage, respectively.
Dependencies are inferred from the claim text.