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US 6,188,598 B1Granted
Reducing impact of coupling noise
AssigneeInfineon Technologies North America Corp.
InventorsGerhard Mueller, Ulrike Gruening
Life of this patent
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Abstract
An integrated circuit comprising a first bitline pair 310 on a first bitline level which is adjacent to a second bitline pair 320 on a second bitline level is provided. The first bitline pair comprises m twists 340, where m is a whole number≧1 and the second bitline pair comprises n twists 350 and 351, where n is a whole number ≠m. The twists transform coupling noise from adjacent bitline pairs into common mode noise, which results in improved signal margin.
Claims26
An integrated circuit comprising:
- a first signal line pair having first and second signal lines, the first signal line pair includes m number of twists, wherein a twist switches signal line paths of the first and second signal lines;
- a second signal line pair having first and second signal lines;
- a first conductive level on which the first signal line pair is located;
- and
- a second conductive level on which the second signal line pair is located, the first signal line pair electrically isolated from the second signal line pair and wherein the m twists reduces impact of coupling noise between the signal line pairs.
2 more elements
Dependencies are inferred from the claim text.