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AssigneeFujitsu Limited
InventorsMasato Takita, Shinichi Yamada, Masato Matsumiya
Estimating the term…
In a semiconductor memory, sub-decoders in two adjacent sub-decoder groups are mirror-arranged with respect to the boundary between the two blocks. Sub-select lines are cross-connected to the sub-decoders in one sub-decoder group. This permits all sub-select lines connected to the two adjacent sub-decoder groups to be sequentially selected in a certain direction in accordance with a sequentially incremented address. Even when shift redundancy processing is performed, the order of selection of these sub-select lines does not reverse itself owing to the mirror arrangement.
A semiconductor memory comprising:
A semiconductor memory comprising:
A semiconductor memory comprising:
Dependencies are inferred from the claim text.
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With improved access time or stability: by adjacent switching
Arrangements for selecting an address in a digital store: using a sequential addressing device, e.g. shift register, counter
Arrangements for selecting an address in a digital store: decoders
Arrangements for selecting an address in a digital store: word line organisation; Word line lay-out
Term ended 31 Mar 2020 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
1. Field of the Invention
The present invention relates to semiconductor memories, particularly to a semiconductor memory, such as a synchronous dynamic random-access memory (to be referred to as SDRAM hereinafter), using a shift redundancy system and formed by arranging decoding circuits of adjacent select lines (word lines) in a mirror image for the purpose of scale down.
2. Description of the Related Art
FIGS. 1A and 1B are plan views showing an example of the effect of space reduction obtained by a mirror arrangement of decoding circuits;
FIG. 2 is a plan view showing the order of selection of sub-select lines in address increment in a conventional semiconductor memory;
FIG. 3 is a plan view showing the order of selection of sub-select lines when arithmetically processed addresses are input in the conventional semiconductor memory;
First Embodiment
The first embodiment of the present invention will be described below with reference to drawings. FIG. 5 is a plan view showing an outline of the arrangement of a cell array block unit of SDRAM as a semiconductor memory according to the first embodiment. FIGS. 6A to 6D are schematic views showing the connections between sub-decoders and sub-select lines in the cell array block unit of the SDRAM shown in FIG. 5. Referring to FIGS. 6A to 6D, two sets of four sub-decoders are mirror-arranged and sub-decoders in each set are not mirror-arranged, for the sake of simplicity.
First, the arrangement of the SDRAM will be described with reference to FIG. 5. In this SDRAM, a hierarchical word line system is used to perform ⅛ selection of sub-select lines from one main select line. Eight sub-decoders for this ⅛ selection are arranged such that four sub-decoders are placed at each end of a cell array, and eight sub-select lines are driven in an interdigitated pattern. As in the semiconductor memory explained with reference to FIGS. 2 to 4, sub-decoders are mirror-arranged, and a shift redundancy system is used as a defect remedy system for main select lines.