Layout for semiconductor memory including multi-level sensing

In a semiconductor memory, a data path comprising:

• a first differential bit-line pair spanning plural memory cells of a first bank including a first memory cell;
• a first primary sense amplifier coupled between the first differential bit-line pair and coupled to supply a first differential output on a second differential bit-line pair spanning a first group of banks including the first bank, but not a second group of banks disjoint from the first group;
• and
• a first secondary sense amplifier coupled between the second differential bit-line pair and coupled to supply a fall-voltage swing output on a data line, wherein the data line spans the second group of banks.

A method of reducing a difference between minimum and maximum delay paths in a semiconductor memory, the method comprising:

• providing plural submodules each including an array of memory cells and primary sense amplifiers coupled to respective ones of the memory cells by local bit-lines,
• spanning a first subset of the submodules with first bit-line pairs coupled to outputs of the primary sense amplifiers of the first subset of submodules;
• spanning a second subset of the submodules with second bit-line pairs coupled to outputs of the primary sense amplifiers of the second subset of submodules, the second bit-line pairs disjoint from the first bit-line pairs;
• and
• placing secondary sense amplifiers between the first and second subsets of submodules, the secondary sense amplifiers input coupled to respective of the first and second bit-line pairs and output coupled to respective data lines,
• wherein individual ones of the data lines span one, but not both, of the first and second subsets of submodules.

A method of reducing power consumption in a semiconductor memory including plural submodules each including an array of memory cells and primary sense amplifiers coupled to respective ones of the memory cells by local bit-lines, the method comprising:

• spanning a first subset of the submodules with first bit-line pairs;
• spanning a second subset of the submodules with second bit-line pairs disjoint from the first bit-line pairs;
• placing secondary sense amplifiers between the first and second subsets of submodules, the secondary sense amplifiers being input coupled to respective of the first and second bit-line pairs and being output coupled to respective data lines,
• wherein the primary sense amplifiers are coupled to drive low-voltage-swing differential signals onto corresponding of the first and second bit-line pairs.

A method of improving access time in a semiconductor memory including plural submodules each including an array of memory cells and primary sense amplifiers coupled to respective ones of the memory cells by local bit-lines, the method comprising:

• spanning a first subset of the submodules with first bit-line pairs;
• spanning a second subset of the submodules with second bit-line pairs disjoint from the first bit-line pairs;
• placing secondary sense amplifiers between the first and second subsets of submodules, the secondary sense amplifiers being input coupled to respective of the first and second bit-line pairs and being output coupled to respective data lines;
• wherein wire delay along signal paths from individual of the memory cells is reduced by operating the secondary sense amplifiers as repeaters;
• and
• wherein maximum to minimum variations round-trip signal paths are reduced by said secondary sense amplifier placement.