US 6,188,594 B1Granted

Reduced-pitch 6-transistor NMOS content-addressable-memory cell

AssigneeNeoMagic Corp.

InventorAdrian E. Ong

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Abstract

A content-addressable memory (CAM) cell uses only n-channel (NMOS) transistors. A total of six transistors (6T) are used in the cell. Dynamic storage and differential sensing are used. A pair of bit lines carry true and complement data. A word line connected to the gates of pass transistors couples the bit lines to gates of storage transistors. The sources of the storage transistors are grounded. Charge is dynamically stored on the gates of the storage transistors when the pass transistors are turned off. One storage transistor has a gate charged to a high voltage and is thus on, while the other storage transistor has its gate discharged to a low voltage and is thus off. The drains of the storage transistors are connected to a match line through a pair of match transistors. The gates of the match transistors are connected to the bit lines. During a compare operation, the test data and its complement are applied to the bit lines, turning one of the match transistors on and the other off. The match transistors and storage transistors form two series connections to the match line. When both a match transistor and a storage transistor in series are on, the match line is discharged, indicating a mismatch. An exclusive-OR (XOR) function is performed by the match and storage transistors. The match transistors can be cross-connected to the opposite bit lines to match data polarity for writes.

Claims14

Dependent claims

A dynamic-storage, differential-access content-addressable memory (CAM) cell comprising:

a pair of bit lines including a true bit line and a complement bit line, for conducting a data bit and a complement of the data bit to the CAM cell;
a word line for indicating when to write data from the bit lines to the CAM cell;
a first storage transistor having a first gate for dynamically storing a state of the CAM cell;
a second storage transistor having a second gate for dynamically storing a complement of the state of the CAM cell;
a first pass transistor having a gate controlled by the word line, for connecting the true bit line to the first gate during a write operation;
a second pass transistor having a gate controlled by the word line, for connecting the complement bit line to the second gate during the write operation;
a match line;
a first match transistor, coupled to the first storage transistor, for discharging current from the match line to the first storage transistor during a compare operation, having a gate controlled by a first bit line of the pair of bit lines, the first bit line receiving a test data bit during the compare operation;
and
a second match transistor, coupled to the second storage transistor, for discharging current from the match line to the second storage transistor during the compare operation, having a gate controlled by a second bit line of the pair of bit lines, the second bit line receiving a complement of the test data bit during the compare operation;
wherein when the first storage transistor is charged when the CAM cell was written to a high state, the match line is discharged to indicate a mis-match when the first match transistor is activated by the first bit line being in a high state;
wherein when the second storage transistor is charged when the CAM cell was written to a low state, the match line is discharged to indicate a mis-match when the second match transistor is activated by the second bit line being in a high state;
wherein the match line remains high when the test data bit matches the state of the CAM cell,
a pair of read bit lines including a true read bit line and a complement read bit line, for differentially sensing the state of the CAM cell during a read operation;
a read word line for indicating when a read operation is reading the state of the CAM cell;
a first read transistor, having a gate controlled by the read word line, for connecting a drain of the first storage transistor to the true read bit line during the read operation;
and
a second read transistor, having a gate controlled by the read word line, for connecting a drain of the second storage transistor to the complement read bit line during the read operation,
whereby the drains of the first and second storage transistors are sensed during the read operation, the CAM cell containing 8 transistors.

16 more elements

A memory cell with a compare gate comprising:

a pair of bit lines including a true bit line and a complement bit line, for conducting a data bit and a complement of the data bit to the memory cell;
a word line for indicating when to write data from the bit lines to the memory cell;
first storage transistor means having a first gate for dynamically storing a state of the memory cell;
second storage transistor means having a second gate for dynamically storing a complement of the state of the memory cell;
first pass transistor means having a gate controlled by the word line, for connecting the true bit line to the first gate during a write operation;
second pass transistor means having a gate controlled by the word line, for connecting the complement bit line to the second gate during the write operation;
a match line;
first match transistor means, coupled to the first storage transistor means, for discharging current from the match line to the first storage transistor means during a compare operation, having a gate controlled by a first bit line of the pair of bit lines, the first bit line receiving a test data bit during the compare operation;
and
second match transistor means, coupled to the second storage transistor means, for discharging current from the match line to the second storage transistor means during the compare operation, having a gate controlled by a second bit line of the pair of bit lines, the second bit line receiving a complement of the test data bit during the compare operation;
wherein the first bit line is the complement bit line;
wherein the second bit line is the true bit line;
wherein the memory cell is written to the high state when the true bit line has a higher voltage than the complement bit line
wherein when the test data is in the high state, the true bit line is driven with a higher voltage than the complement bit line,
whereby the true bit line carries true write data for the write operation and true test data for compare operation, the memory cell being cross-connected and whereby the first and second storage transistor means and the first and second match transistor means are a compare gate.

12 more elements

A memory cell with a compare gate comprising:

a pair of bit lines including a true bit line and a complement bit line, for conducting a data bit and a complement of the data bit to the memory cell;
a word line for indicating when to write data from the bit lines to the memory cell;
first storage transistor means having a first gate for dynamically storing a state of the memory cell;
second storage transistor means having a second gate for dynamically storing a complement of the state of the memory cell;
first pass transistor means having a gate controlled by the word line, for connecting the true bit line to the first gate during a write operation;
second pass transistor means having a gate controlled by the word line, for connecting the complement bit line to the second gate during the write operation;
a match line;
first match transistor means, coupled to the first storage transistor means, for discharging current from the match line to the first storage transistor means during a compare operation, having a gate controlled by a first bit line of the pair of bit lines, the first bit line receiving a test data bit during the compare operation;
and
second match transistor means, coupled to the second storage transistor means, for discharging current from the match line to the second storage transistor means during the compare operation, having a gate controlled by a second bit line of the pair of bit lines, the second bit line receiving a complement of the test data bit during the compare operation;
wherein the state of the memory cell stored on the first gate of the first storage transistor means is lost after a period of time due to leakage;
wherein the memory cell is periodically re-written with the state to refresh the state of the memory cell before the state is lost,
wherein the first and second pass transistor means each comprise a series-connected pair of transistors with a gate connected to a write-enable signal,
whereby the memory cell has a write-enable control and whereby the memory cell is periodically refreshed and the first and second storage transistor means and the first and second match transistor means are a compare gate.

11 more elements

Dependencies are inferred from the claim text.