Internal row sequencer for reducing bandwidth and peak current requirements in a display driver circuit

A display driver circuit for receiving data and data load instructions from a system, and for driving a display having a plurality of data input lines and a first plurality of word lines, each word line being associated with a portion of said display, such that write signals asserted on said word lines cause data asserted on said data input lines to be loaded into said associated portions of said display, said display driver circuit comprising:

• data processing means responsive to said data load instructions and operative upon receipt of each said data load instruction to receive a first predetermined quantity of data from said system, to accumulate said data, and to assert the accumulated data on said data input lines of said display when a second predetermined quantity of data is accumulated;
• and
• display portion selecting means for receiving said data load instructions and for generating write signals for causing data to be loaded into said associated portions of said display, said display portion selecting means being operative to assert a first write signal on a first one of said word lines causing data initially asserted on said data input lines to be loaded into an associated portion of said display, and to determine from said data load instructions when a third predetermined quantity of data has been subsequently asserted on said data input lines, and in response thereto, asserting a second write signal onto a second word line associated with a second portion of said display, said display portion selecting means thereafter continuing to determine each time a third predetermined quantity of data has been subsequently asserted on said data input lines, and in response thereto, asserting a subsequent write signal onto a subsequent word line associated with a subsequent portion of said display, until all incoming data has been received.