US 6,188,345 B1Granted

High speed delta-sigma A/D converter using a quantized USM negative feedback loop

AssigneeTexas Instruments Incorporated

InventorsCharles L. McDonald, T. R. Viswanathan, Krishnaswamy Nagaraj

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Abstract

A high speed sigma-delta A/D converter for a sequence of analog samples xn (n=0,1,2, . . . N−1) has an input, a plurality N−1 of phase clocks Φn, a plurality of sample-hold circuits 40n, a plurality N−1 of circuit stages, and a D/A converter. The input receives the analog samples xn. The sample-hold circuits 40n are coupled to the input and each responds to a respective phase clock Φn to sample and hold a corresponding analog sample Xn. Each circuit stage n has a summer 42n and a quantizer 44n. The summer has (i) a data input receiving a data signal (xn) from a corresponding sample-hold circuit 40n, (ii) a prior sum signal (wn−1) input, and (iii) a prior quantized signal (yn−1) negative input. The summer 42n produces a sum signal (wn=xn+wn−−Yn−1) at a summer output. The quantizer 44n is coupled to the summer's output for quantizing the sum signal wn into a quantized sum signal yn. The D/A converter provides the N−1 (last) stage's quantized sum signal yN−1 to the prior sum signal input of the 0 (first) stage's summer 421.

Claims7

Dependent claims

A sigma-delta A/D converter, comprising:

a plurality of sample-hold circuits coupled to receive an analog input signal, each responsive to a respective one of a plurality of phase clocks to sample and hold a corresponding sample of the analog input signal;
a plurality of circuit stages arranged in a sequence, each circuit stage associated with one of the plurality of sample-hold circuits, a first one of the plurality of circuit stages comprising:
a summer having a first input receiving a data signal from a first one of the plurality of sample-hold circuits, a second input receiving an initial prior sum signal, and a negative input receiving an initial prior quantized sum signal, for producing a sum signal at a summer output;
and
a quantizer coupled to the summer output for quantizing the sum signal into a quantized sum signal;
and wherein each of the other of the plurality of circuit stages comprise:
a summer having a first input receiving a data signal from a corresponding sample-hold circuit, a second input receiving a prior sum signal from the summer output of the prior circuit stage in the sequence, and a negative input receiving a prior quantized sum signal from the quantizer of the prior circuit stage in the sequence, for producing a sum signal at a summer output;
and
a quantizer coupled to the summer output for quantizing the sum signal into a quantized sum signal.

6 more elements

Dependencies are inferred from the claim text.