US 6,188,272 B1Granted

Filter circuit

AssigneeKabushiki Kaisha Toshiba

InventorTakashi Fujiwara

Life of this patent

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Abstract

Provided is a circuit arrangement for attaining an all-pass filter characteristics which have been conventionally attained by bipolar transistors, by using MIS transistors. An alternating-current signal is input to an input terminal of an inversion circuit having a two-fold amplification function through a low-pass filter. When output from the inversion circuit is input to a gate of a lower transistor of two MIS transistors cascaded and an inverted signal of the alternating-current signal is input to a gate of an upper transistor of the two MIS transistors cascaded, the alternating-current signal is subtracted from the output from the inversion circuit. In this manner, the all-pass filter is formed.

Claims18

Dependent claims

A filter circuit comprising:

a first MIS transistor having a first source, a first drain, a first gate, and a channel of one conductivity type;
an input terminal connected to the first gate of the first MIS transistor;
a first power supply terminal connected to the first source of the first MIS transistor;
a second MIS transistor having a second source, a second drain, a second gate, and a channel of the one conductivity type, the second source being connected to the first drain of the first MIS transistor;
a first bias supply circuit connected to the second gate of the second MIS transistor;
a second power supply terminal connected to the second drain of the second MIS transistor;
a third MIS transistor having a third source, a third drain, a third gate, and a channel of the one conductivity type, the third source being connected to the first power supply terminal;
a resistor connected between the third gate of the third MIS transistor and the input terminal;
a capacitor connected between the third gate of the third MIS transistor and the first power supply terminal;
a fourth MIS transistor having a fourth source, a fourth drain, a fourth gate, and a channel of the one conductivity type, the fourth source being connected to the third drain of the third MIS transistor, the fourth drain being connected to the second power supply terminal, and a width/length ratio of the fourth gate being substantially ¼ of that of the third gate of the third MIS transistor;
a second bias supply circuit connected to the fourth gate of the fourth MIS transistor;
a fifth MIS transistor having a fifth source, a fifth drain, a fifth gate, and a channel of the one conductivity type, the fifth source being connected to the first power supply terminal, and the fifth gate being connected to the fourth source of the fourth MIS transistor;
an output terminal connected to the fifth drain of the fifth transistor;
and
a sixth MIS transistor having a sixth source, a sixth drain, a sixth gate, and a channel of the one conductivity type, the sixth gate being connected to the second source of the second MIS transistor, the sixth source being connected to the fifth drain of the fifth MIS transistor and the output terminal, and the sixth drain being connected to the second power supply terminal.

12 more elements

A filter circuit comprising:

a first MIS transistor having a first source, a first drain, a first gate, and a channel of one conductivity type;
an input terminal connected to the first gate of the first MIS transistor;
a first power supply terminal connected to the first source of the first MIS transistor;
a second MIS transistor having a second source, a second drain, a second gate, and a channel of the one conductivity type, the second source being connected to the first drain of the first MIS transistor;
a first bias supply circuit connected to the second gate of the second MIS transistor;
a second power supply terminal connected to the second drain of the second MIS transistor;
a third MIS transistor having a third source, a third drain, a third gate, and a channel of the one conductivity type, the third source being connected to the first power supply terminal;
a resistor connected between the third gate of the third MIS transistor and the input terminal;
a capacitor connected between the third gate of the third MIS transistor and the first power supply terminal;
a fourth MIS transistor having a fourth source, a fourth drain, a fourth gate, and a channel of the one conductivity type, the fourth gate being connected to the first bias supply circuit, the fourth source being connected to the third drain of the third MIS transistor, and the fourth drain being connected to the second power supply terminal;
a fifth MIS transistor having a fifth source, a fifth drain, a fifth gate, and a channel of the one conductivity type, the fifth source being connected to the first power supply terminal, and the fifth gate being connected to the third gate of the third MIS transistor;
a sixth MIS transistor having a sixth source, a sixth drain, a sixth gate, and a channel of the one conductivity type, the sixth source being connected to the fifth drain of the fifth MIS transistor, the sixth gate being connected to the fourth source of the fourth MIS transistor, and the sixth drain being connected to the second power supply terminal;
a seventh MIS transistor having a seventh source, a seventh drain, a seventh gate, and a channel of the one conductivity type, the seventh source being connected to the first power supply terminal, and the seventh gate being connected to the sixth source of the sixth MIS transistor;
an output terminal connected to the seventh drain of the seventh MIS transistor;
and
an eighth MIS transistor having an eighth source, an eighth drain, an eighth gate, and a channel of the one conductivity type, the eighth gate being connected to the second source of the second MIS transistor, the eighth source being connected to the seventh drain of the seventh MIS transistor and the output terminal, and the eighth drain being connected to the second power supply terminal.

13 more elements

A filter circuit comprising:

a first MIS transistor having a first source, a first drain, a first gate, and a channel of one conductivity type;
an input terminal connected to the first gate of the first MIS transistor;
a first power supply terminal connected to the first source of the first MIS transistor;
a second MIS transistor having a second source, a second drain, a second gate, and a channel of the one conductivity type, the second source being connected to the first drain of the first MIS transistor;
a first bias supply circuit connected to the second gate of the second MIS transistor;
a second power supply terminal connected to the second drain of the second MIS transistor;
a third MIS transistor having a third source, a third drain, a third gate, and a channel of the one conductivity type, the third source being connected to the first power supply terminal;
a low pass filter connected between the third gate of the third MIS transistor and the input terminal;
a fourth MIS transistor having a fourth source, a fourth drain, a fourth gate, and a channel of the one conductivity type, the fourth source being connected to the third drain of the third MIS transistor, the fourth drain being connected to the second power supply terminal, and a width/length ratio of the fourth gate being substantially ¼ of that of the third gate of the third MIS transistor;
a second bias supply circuit connected to the fourth gate of the fourth MIS transistor;
a fifth MIS transistor having a fifth source, a fifth drain, a fifth gate, and a channel of the one conductivity type, the fifth source being connected to the first power supply terminal, and the fifth gate being connected to the fourth source of the fourth MIS transistor;
an output terminal connected to the fifth drain of the fifth transistor;
and
a sixth MIS transistor having a sixth source, a sixth drain, a sixth gate, and a channel of the one conductivity type, the sixth gate being connected to the second source of the second MIS transistor, the sixth source being connected to the fifth drain of the fifth MIS transistor and the output terminal, and the sixth drain being connected to the second power supply terminal.

11 more elements

A filter circuit comprising:

a first MIS transistor having a first source, a first drain, a first gate, and a channel of one conductivity type;
an input terminal connected to the first gate of the first MIS transistor;
a first power supply terminal connected to the first source of the first MIS transistor;
a second MIS transistor having a second source, a second drain, a second gate, and a channel of the one conductivity type, the second source being connected to the first drain of the first MIS transistor;
a first bias supply circuit connected to the second gate of the second MIS transistor;
a second power supply terminal connected to the second drain of the second MIS transistor;
a third MIS transistor having a third source, a third drain, a third gate, and a channel of the one conductivity type, the third source being connected to the first power supply terminal;
a low pass filter connected between the third gate of the third MIS transistor and the input terminal;
a fourth MIS transistor having a fourth source, a fourth drain, a fourth gate, and a channel of the one conductivity type, the fourth gate being connected to the first bias supply circuit, the fourth source being connected to the third drain of the third MIS transistor, and the fourth drain being connected to the second power supply terminal;
a fifth MIS transistor having a fifth source, a fifth drain, a fifth gate, and a channel of the one conductivity type, the fifth source being connected to the first power supply terminal, and the fifth gate being connected to the third gate of the third MIS transistor;
a sixth MIS transistor having a sixth source, a sixth drain, a sixth gate, and a channel of the one conductivity type, the sixth source being connected to the fifth drain of the fifth MIS transistor, the sixth gate being connected to the fourth source of the fourth MIS transistor, and the sixth drain being connected to the second power supply terminal;
a seventh MIS transistor having a seventh source, a seventh drain, a seventh gate, and a channel of the one conductivity type, the seventh source being connected to the first power supply terminal, and the seventh gate being connected to the sixth source of the sixth MIS transistor;
an output terminal connected to the seventh drain of the seventh MIS transistor;
and
an eighth MIS transistor having an eighth source, an eighth drain, an eighth gate, and a channel of the one conductivity type, the eighth gate being connected to the second source of the second MIS transistor, the eighth source being connected to the seventh drain of the seventh MIS transistor and the output terminal, and the eighth drain being connected to the second power supply terminal.

12 more elements

Dependencies are inferred from the claim text.

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Abstract

A filter circuit comprising:

a first MIS transistor having a first source, a first drain, a first gate, and a channel of one conductivity type;
an input terminal connected to the first gate of the first MIS transistor;
a first power supply terminal connected to the first source of the first MIS transistor;
a second MIS transistor having a second source, a second drain, a second gate, and a channel of the one conductivity type, the second source being connected to the first drain of the first MIS transistor;
a first bias supply circuit connected to the second gate of the second MIS transistor;
a second power supply terminal connected to the second drain of the second MIS transistor;
a third MIS transistor having a third source, a third drain, a third gate, and a channel of the one conductivity type, the third source being connected to the first power supply terminal;
a resistor connected between the third gate of the third MIS transistor and the input terminal;
a capacitor connected between the third gate of the third MIS transistor and the first power supply terminal;
a fourth MIS transistor having a fourth source, a fourth drain, a fourth gate, and a channel of the one conductivity type, the fourth source being connected to the third drain of the third MIS transistor, the fourth drain being connected to the second power supply terminal, and a width/length ratio of the fourth gate being substantially ¼ of that of the third gate of the third MIS transistor;
a second bias supply circuit connected to the fourth gate of the fourth MIS transistor;
a fifth MIS transistor having a fifth source, a fifth drain, a fifth gate, and a channel of the one conductivity type, the fifth source being connected to the first power supply terminal, and the fifth gate being connected to the fourth source of the fourth MIS transistor;
an output terminal connected to the fifth drain of the fifth transistor;
and
a sixth MIS transistor having a sixth source, a sixth drain, a sixth gate, and a channel of the one conductivity type, the sixth gate being connected to the second source of the second MIS transistor, the sixth source being connected to the fifth drain of the fifth MIS transistor and the output terminal, and the sixth drain being connected to the second power supply terminal.

12 more elements