US 6,188,269 B1 · Circuits and methods for generating bias voltages to control output stage idle currents

Abstract

The circuits and methods of the present invention provide rail-to-rail output stages that cancel the non-linear components of the transconductances of transistors used in the output stages, that allow the idling current in the output stages to be controlled by external current sources and device size ratios, and that enable the idling current in the output stages to be maintained independently of manufacturing processes, temperature, and power supply voltages. The output stages generally comprise a complementary subcircuit, a current mirror and an output driver. The output stages receive an input signal and a bias voltage from an external source and responsively produce a push current that feeds current into a load and a pull current that pulls current from the load. When the push current matches the pull current, the output stages are said to be “idling.” The bias voltage controls the idling current. By mimicking the voltages and currents produced in the output stages using similar components, a bias voltage generation circuit provides a bias voltage that enables the idling point to be maintained in the output stages independently of manufacturing processes, temperature, and power supply voltages.

Claims28

Dependent claims

A circuit that generates a bias voltage for an output stage having an idling point at which an idling current is produced when an input signal equals a DC voltage and a bias input equals said bias voltage, comprising:

a first current source that produces a first current which is proportional to said idling current;
a transistor that passes a first current amount that includes at least a portion of said first current, that controls said first current amount being passed in response to an input voltage, and that passes said first current amount equal to said first current when said input voltage is equal to said DC voltage;
a current mirror that has a current mirror output which passes a second current amount including at least a portion of a second current, and that controls said second current amount being passed in response to a subcircuit current;
a second current source that produces said second current which is proportional to said idling current and that causes said input voltage to change in response to said second current amount being passed by said current mirror;
and
a complementary subcircuit that has a first input that is controlled by said input voltage, a second input that is responsive to whether said transistor is passing said first current amount equal to said first current, and an output that produces said subcircuit current in an amount that is responsive to said first input and said second input of said subcircuit, such that when said subcircuit produces said subcircuit current that causes said current mirror to pass said second current amount equal to said second current and said input voltage equals said DC voltage, said bias voltage is present at said second input.

3 more elements

A method for generating a bias voltage for an output stage having an idling point at which an idling current is produced when an input signal equals a DC voltage and a bias input equals said bias voltage, comprising:

producing a first current that is proportional to said idling current using a first current source;
in a transistor, passing a first current amount including at least a portion of said first current, controlling said first current amount being passed in response to an input voltage, and passing said first current amount equal to said first current when said input voltage is equal to said DC voltage;
in a current mirror having a current mirror output, passing a second current amount including at least a portion of a second current, and controlling said second current amount being passed in response to a subcircuit current;
in a second current source, producing said second current that is proportional to said idling current and causing said input voltage to change in response to said second current amount being passed by said current mirror;
and
in a complementary subcircuit having a first input controlled by said input voltage and a second input responsive to whether said transistor is passing said first current amount equal to said first current, producing said subcircuit current in an amount responsive to said first input and said second input of said subcircuit such that when said subcircuit produces said subcircuit current causing said current mirror to pass said second current amount equal to said second current and said input voltage equals said DC voltage, said bias voltage is present at said second input.

3 more elements

Dependencies are inferred from the claim text.

Circuits and methods for generating bias voltages to control output stage idle currents

Life of this patent

Circuits and methods for generating bias voltages to control output stage idle currents

Life of this patent

Abstract

Claims28