Synchronous polyphase clock distribution system
AssigneeSun Microsystems, Inc.
InventorIvan E. Sutherland
Life of this patent
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Abstract
A clock distribution system is described for providing synchronous clock signals in as many phases as a designer of a given circuit finds useful. The clock distribution system acknowledges timing constraints of the controlled system, and adjusts the clock phase appropriately to meet the needs of the local data circuits using the clock signals. The clock distribution system includes stages which are coupled to appropriate portions of the datapath and to each other for controlling the datapath and provide information about clock signal timing to each other.
Claims13
A clock distribution system for providing clock signals in a plurality of phases to an associated circuit, the system comprising:
- a first clock signal circuit for providing a first clock signal which transitions between a first state and a second state;
- a second clock signal circuit for providing a second clock signal which transitions between the first state and the second state;
- a third clock signal circuit for providing a third clock signal which transitions between the first state and the second state;
- the first clock signal circuit providing a first control signal to the second clock signal circuit when the first clock signal changes from the first state to the second state thereby permitting the second clock signal to change from the first state to the second state;
- the second clock signal circuit providing a second control signal to the first clock signal circuit when the second clock signal circuit responds to the first control signal and transitions from the first state to the second state, the second control signal thereby permitting the first clock signal to change from the second state back to the first state;
- the third clock signal circuit providing a third control signal to the first clock signal circuit when the third clock signal changes from the first state to the second state thereby permitting the first clock signal to change from the first state to the second state;
- and
- the first clock signal circuit providing a fourth control signal to the third clock signal circuit when the first clock signal circuit responds to the third control signal and transitions from the first state to the second state thereby permitting the third clock signal to change from the second state back to the first state.
In a clock distribution system for providing clock signals in a plurality of phases to an associated circuit, a first clock signal circuit coupled to separate a second clock signal circuit from a third clock signal circuit, the first clock signal circuit comprising:
- a first input node coupled to receive signals from the third clock signal circuit;
- a second input node coupled to receive signals from the second clock signal circuit;
- a first output node coupled to provide signals to the second clock signal circuit;
- a second output node coupled to provide signals to the third clock signal circuit;
- and
- the first clock signal circuit coupled to the first and second input and output nodes for controlling the second and the third clock signal circuits.
Dependencies are inferred from the claim text.