Programmable delay generator and application circuits having said delay generator

A programmable delay generator comprising:

• ramp wave voltage generator receiving a S-enable signal, a S-set data S and a clock signal for providing a ramp wave voltage Vs across a first capacitor having a capacitance C1 which receives a current SI0 proportional to a value S synchronized with a first clock signal after said S-enable signal is provided, so that said ramp voltage is equal to Vs=(SI0/C)t where t is time after said first clock signal is provided;
• a threshold voltage generator receiving a K-enable signal which is enabled before said S-enable signal in advance at least by m number of clocks (m is an integer), a set data K, and a clock signal for providing a threshold voltage VK across a second capacitor having a capacitance C2 which receives a current KI0 proportional to value K during time mT, where T is a period of the clock signal for providing a threshold VK across the second capacitor, so that the threshold voltage VK is equal to VK=(KI0/C)mt;
• a delay time generation means which compares said ramp wave voltage Vs with said threshold voltage VK so that an output signal having a predetermined pulse width provided when said VS coincides with said VK with delay time td after said first clock where td=(K/S)mT and
• where said first capacitor and said second capacitor are discharged by a predetermined S-leak signal and a predetermined K-leak signal after said output signal is provided.

A programmable delay generator comprising:

• a ramp wave generator receiving a S-enable signal, a S-set data S and a clock signal for providing a ramp wave voltage VSC across a first capacitor having capacitance C1 which receives a current I0 during a first clock signal t0 after said S-enable signal is provided so that voltage VSC=(I0/C1)t is obtained across said first capacitor, where t is a time after a first clock signal t0, and said voltage VSC is related to a ramp voltage Vs such that Vs=(S/M)(I0/C)t;
• a threshold voltage generator receiving a K-enable signal which is enabled before said S-enable signal in advance at least by m number of clocks (m is an integer), a threshold voltage Vkc across a second capacitor having a second capacitance C2 and which receives the current I0 during time mT, where T is a period of a clock signal, so that a voltage Vkc=(I0/C2)mT is obtained across said second capacitor and said voltage Vkc is maintained across said second capacitor, and the voltage Vkc is related to a threshold voltage Vk such that Vk=(K/M)(I0/C2)mT;
• a delay time generation means which compares said ramp wave voltage Vs with said threshold voltage Vk so that an output signal having a predetermined pulse width is provided when said Vs coincides with said Vk with a delay time td after said first clock signal t0 such that td=(K/S)mT;
• wherein said first capacitor and said second capacitor are discharged by a predetermined S-leak signal and a predetermined K-leak signal after said output signal is provided.

A frequency synthesizer comprising:

• an accumulator receiving a clock signal and a set data S for accumulating said set data S synchronized with said clock signal;
• a data converter for calculating a set data K with (2n−1−θp), where θp is a previous output data θ of said accumulator by 1 clock period before the most significant bit θMSB rises;
• a control circuit which receives an output θ of said accumulator and provides a K-enable signal which rises before θMSB by one clock period, and has a pulse width equal to one clock period;
• and
• a programmable delay generator which receives said set data S, set data K provided by said data converter, said K-enable signal provided by said control circuit, and an S-enable signal which is the most significant bit θMSB of an output data θ of said accumulator;
• wherein said programmable delay generator comprises
• a first ramp wave generator and a second ramp wave generator, each having a capacitor of the same capacitance as each other for generating a ramp wave by flowing a current in said capacitor, each of them operating with external common clock pulses, and each of them providing a potential gradient and a final potential incorporated with an external set data,
• a comparator for comparing an output (VS) of the first ramp wave generator and an output (VK) of the second ramp wave generator so that an output pulse is provided when the outputs of the two ramp wave generators coincide with each other,
• said first ramp wave generator providing a first ramp voltage (VS) upon receipt of a first set data (S) at a predetermined time (t0),
• said second ramp wave generator providing a threshold voltage (VK) upon receipt of a second set data (K) at a time which precedes said predetermined time by at least one clock time (T), and
• said comparator providing an output pulse delayed by delay time (td) which is proportional to ratio of said second set data and said first set data from said predetermined time.

A frequency synthesizer comprising:

• an accumulator receiving a clock signal and a set data S for accumulating said set data S synchronized with said clock signal;
• a data converter which receives an output data θ and an overflow signal of said accumulator and calculates a set data K with (2n−θ);
• a control circuit which receives an output θ of said accumulator and provides a K-enable signal which rises one clock time before said overflow signal rises, and has a pulse width equal to one clock period;
• and
• a programmable delay generator which receives said set data S, said set data K provided by said data converter, said K-enable signal provided by said control circuit, and an S-enable signal which is the overflow signal of an output data θ of said accumulator;
• wherein said programmable delay generator comprises
• a first ramp wave generator and a second ramp wave generator, each having a capacitor of the same capacitance as each other for generating a ramp wave by flowing a current in said capacitor, each of them operating with external common clock pulses, and each of them providing a potential gradient and a final potential incorporated with an external set data,
• a comparator for comparing an output (VS) of the first ramp wave generator and an output (VK) of the second ramp wave generator so that an output pulse is provided when the outputs of the two ramp wave generators coincide with each other,
• said first ramp wave generator providing a first ramp voltage (VS) upon receipt of a first set data (S) at a predetermined time (t0),
• said second ramp wave generator providing a threshold voltage (VK) upon receipt of a second set data (K) at a time which precedes said predetermined time by at least one clock time (T), and
• said comparator providing an output pulse delayed by delay time (td) which is proportional to ratio of said second set data and said first set data from said predetermined time.

A frequency synthesizer comprising:

• an accumulator receiving a clock signal and a set data S for accumulating said set data S synchronized with said clock signal;
• a data converter which receives an output data θ and an OFD signal which is one clock delayed signal of an overflow signal of said accumulator and calculates a set data K with (S−θ);
• a control circuit which receives an output θ and said OFD signal of said accumulator and provides a K-enable signal which rises one clock time before said overflow signal rises, and has a pulse width equal to one clock period;
• and
• a programmable delay generator which receives said set data S, said set data K provided by said data converter, said K-enable signal provided by said control circuit, and an S-enable signal which is the OFD signal of an output data θ of said accumulator;
• wherein said programmable delay generator comprises
• a first ramp wave generator and a second ramp wave generator, each having a capacitor of the same capacitance as each other for generating a ramp wave by flowing a current in said capacitor, each of them operating with external common clock pulses, and each of them providing a potential gradient and a final potential incorporated with an external set data,
• a comparator for comparing an output (VS) of the first ramp wave generator and an output (VK) of the second ramp wave generator so that an output pulse is provided when the outputs of the two ramp wave generators coincide with each other,
• said first ramp wave generator providing a first ramp voltage (VS) upon receipt of a first set data (S) at a predetermined time (t0),
• said second ramp wave generator providing a threshold voltage (VK) upon receipt of a second set data (K) at a time which precedes said predetermined time by at least one clock time (T), and
• said comparator providing an output pulse delayed by delay time (td) which is proportional to ratio of said second set data and said first set data from said predetermined time.

A frequency multiplier receiving an input signal having period T and providing an output signal with N/M times of frequency as high as that of said input signal comprising:

• plurality of delay generators each providing a respective delay time d+(kM/N)T, where d is an arbitrary time, N is an integer larger than 2, M is an integer larger than 1, k is an integer from 0 to N−1;
• a distributor receiving an input signal and providing each of said delay generators a delay timing and
• an OR gate for providing a logical sum of outputs of said delay generators;
• wherein each of said delay generators comprises
• a first ramp wave generator and a second ramp wave generator, each having a capacitor of the same capacitance as each other for generating a ramp wave by flowing a current in said capacitor, each of them operating with external common clock pulses, and each of them providing a potential gradient and a final potential incorporated with an external set data,
• a comparator for comparing an output (VS) of the first ramp wave generator and an output (VK) of the second ramp wave generator so that an output pulse is provided when the outputs of the two ramp wave generators coincide with each other,
• said first ramp wave generator providing a first ramp voltage (VS) upon receipt of a first set data (S) at a predetermined time (t0),
• said second ramp wave generator providing a threshold voltage (VK) upon receipt of a second set data (K) at a time which precedes said predetermined time by at least one clock time (T), and
• said comparator providing an output pulse delayed by delay time (td) which is proportional to ratio of said second set data and said first set data from said predetermined time.

A duty ratio converter comprising:

• a distributor receiving an input pulse having a period T, and providing a plurality of outputs having a rise time and a fall time of said input pulse;
• a plurality of flip-flops switching an output pulse of a same high and low synchronized with an output of said distributor;
• a plurality of delay generators receiving an output of said distributor as a clock signal, and providing said flip-flops an output to control the same high and low;
• wherein each of said delay generators comprises
• a first ramp wave generator and a second ramp wave generator, each having a capacitor of the same capacitance as each other for generating a ramp wave by flowing a current in said capacitor, each of them operating with external common clock pulses, and each of them providing a potential gradient and a final potential incorporated with an external set data,
• a comparator for comparing an output (VS) of the first ramp wave generator and an output (VK) of the second ramp wave generator so that an output pulse is provided when the outputs of the two ramp wave generators coincide with each other,
• said first ramp wave generator providing a first ramp voltage (VS) upon receipt of a first set data (S) at a predetermined time (t0),
• said second ramp wave generator providing a threshold voltage (VK) upon receipt of a second set data (K) at a time which precedes said predetermined time by at least one clock time (T), and
• said comparator providing an output pulse delayed by delay time (td) which is proportional to ratio of said second set data and said first set data from said predetermined time.

A duty ratio converter comprising:

• distributor receiving an input pulse having a period T and providing a rise time and a fall time of said input pulse to a plurality of branches;
• a plurality of delay generators operating with a clock signal provided by said distributor;
• a plurality of flip-flops receiving an output of said delay generator, to provide an output signal switching high and low;
• and
• an OR gate to provide a logical sum of said flip-flops
• wherein each of said delay generators comprises
• a first ramp wave generator and a second ramp wave generator, each having a capacitor of the same capacitance as each other for generating a ramp wave by flowing a current in said capacitor, each of them operating with external common clock pulses, and each of them providing a potential gradient and a final potential incorporated with an external set data,
• a comparator for comparing an output (VS) of the first ramp wave generator and an output (VK) of the second ramp wave generator so that an output pulse is provided when the outputs of the two ramp wave generators coincide with each other,
• said first ramp wave generator providing a first ramp voltage (VS) upon receipt of a first set data (S) at a predetermined time (t0),
• said second ramp wave generator providing a threshold voltage (VK) upon receipt of a second set data (K) at a time which precedes said predetermined time by at least one clock time (T), and
• said comparator providing an output pulse delayed by delay time (td) which is proportional to ratio of said second set data and said first set data from said predetermined time.