Self-reset flip-flop with self shut-off mechanism
AssigneeSun Microsystems, Inc.
InventorsChaim Amir, Heip P. Ngo
Life of this patent
Estimating the term…
Abstract
An electronic system is described for a flip-flop circuit having a data input stage with a clock input and a data input, coupled to an output stage which generates at least one data output, a reset circuit coupled to said data output stage for resetting the logic state of the data outputs to a predetermined desired condition, and a shutoff circuit coupled to said data input stage blocking data input from being acted on by said data input stage. An alternate embodiment includes a data processing circuit with a feedback mechanism coupled with the reset circuit of the flip-flop which informs the flip-flop that data is no longer required.
Claims7
A flip-flop circuit system comprising:
- a data input stage having a clock input, a data input and an input stage output;
- an output stage, having an input coupled to said input stage output, which generates at least one data output;
- a reset circuit, having a reset input coupled to said data output and having a reset output coupled to said output stage, which resets the logic state of said output stage to a predetermined desired condition;
- and
- a shutoff circuit which receives said clock input and said input stage output and generates a shut-off circuit output signal which is presented to said data input stage to disable said data input stage after a predetermined time period.
A method for operating a flip-flop circuit including a data input stage having a data input, a clock input, and input stage output coupled to an output stage having an input coupled to said input stage output and generating at least one data output, a reset circuit coupled to said output stage for resetting the logic state of the data outputs to a predetermined desired condition and a shutoff circuit coupled to said data input stage and said clock input for blocking said data input from being acted on by said data input stage after a predetermined time period, the method comprising:
- causing said data input stage to receive data from a data source;
- causing said output stage to receive data from said data input stage to generate said data output;
- causing said shutoff circuit to disable the data input of said data input stage so that signals present on said data input do not affect the logic state of the output stage;
- and
- causing said reset circuitry to reset the output of said output stage to a predetermined condition.
A method for operating a flip-flop circuit in a data processing circuit, said flip-flop circuit including a data input stage having a data input, a clock input, and input stage output coupled to an output stage having an input coupled to said input stage output and generating at least one data output, a reset circuit coupled to said output stage for resetting the logic state of the data outputs to a predetermined desired condition and a shutoff circuit coupled to said data input stage having said clock input for blocking said data input from being acted on by said data input stage after a predetermined time period, the data processing circuit including a feedback mechanism coupled to said reset circuit, the method comprising:
- causing said data input stage to receive data from a data source;
- causing said output stage to receive data from said data input stage to generate said data output;
- causing said shutoff circuit to disable the data input of said data input stage so that signals present on said data input do not affect the logic state of the output stage;
- causing said reset circuitry to reset the output of said output stage to a predetermined condition;
- and
- causing said feedback mechanism to inform said reset circuit that said data output is no longer required.
Dependencies are inferred from the claim text.