Clock generating circuitry

Clock generating circuitry comprising:

• first frequency multiplying means for multiplying the frequency of a reference clock applied thereto by 2n, where n is a natural integer, and for outputting the frequency-multiplied clock as a first clock signal, said first frequency multiplying means having a first oscillator means for oscillating at a first frequency;
• frequency dividing means for dividing the frequency of the frequency-multiplied clock output by said first frequency multiplying means by 193, and for outputting the frequency-divided clock;
• and
• second frequency multiplying means for multiplying the frequency of the frequency-divided clock from said frequency dividing means by 151, and for outputting the frequency-multiplied clock as a second clock signal, said second frequency multiplying means having a second oscillator means for oscillating at a second frequency which is less than said first frequency.

Clock generating circuitry comprising:

• a first frequency multiplier for multiplying a frequency of a reference clock applied thereto by 2n, where n is a natural integer, and for outputting the frequency-multiplied clock as a first clock;
• said first frequency multiplier including
• a first frequency divider,
• a first phase comparator for comparing a phase of the reference clock with that of a frequency-divided clock generated by the first frequency divider,
• a first charge pump circuit for generating a pulse signal according to the comparison result from the first phase comparator,
• a first low-pass filter for attenuating high-frequency components of said pulse signal from the first charge pump circuit, and
• a first voltage-controlled oscillator for producing a frequency-multiplied clock of a certain frequency that is proportional to an output potential of the first low-pass filter,
• said first frequency divider dividing the frequency of the frequency-multiplied clock from the first voltage-controlled-oscillator by 2n, and outputting the frequency-divided clock to the first phase comparator,
• a second frequency divider for dividing the frequency of the frequency-multiplied clock from the first frequency multiplier by 227, and for outputting the frequency-divided clock;
• and
• a second frequency multiplier for multiplying the frequency of the frequency-divided clock from the second frequency divider by 128 and for outputting the frequency-multiplied clock as a second clock,
• said second frequency multiplier including
• a third frequency divider,
• a second phase comparator for comparing the phase of the frequency-divided clock from the second frequency divider with that of a frequency-divided clock generated by the third frequency divider,
• a second charge pump circuit for generating a pulse signal according to the comparison result from the second phase comparator,
• a second low-pass filter for attenuating high-frequency components of the pulse signal from the second charge pump circuit, and
• a second voltage-controlled oscillator for producing a frequency-multiplied clock of a certain frequency that is proportional to an output potential of the second low-pass filter.