Configurable clock generator
AssigneeCypress Semiconductor Corporation
InventorEric N. Mann
Life of this patent
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Abstract
A circuit and method implement a configurable clock generator comprising a logic circuit, a configurable matrix and a phase-locked loop. The logic circuit may be configured to generate a plurality of control signals. The configurable matrix may comprise a plurality of interconnections that may be configured to (i) receive the plurality of control signals from the logic circuit and (ii) bus the control signals to the phase-locked loop. The plurality of control signals may control the operation of the phase-locked loop. In one example, the logic circuit may comprise a sea of gates logic array.
Claims19
A clock generation circuit comprising:
- a logic circuit configured to generate a plurality of first signals;
- a matrix of programmable interconnections configured to (i) receive said plurality of first signals and one or more second signals and (ii) present one or more of said first signals to a phase-locked loop and one or more of said second signals to an output, in response to the programming of said programmable interconnections;
- and
- said phase-locked loop configured to (i) receive said one or more first signals from the matrix and (ii) present said one or more second signals to said matrix of programmable interconnections, wherein said one or more first signals control the operation of said phase-locked loop.
A clock generation circuit comprising:
- first means for generating a plurality of first signals;
- second means for (i) receiving said plurality of first signals and one or more second signals and (ii) presenting one or more of said first signals to a third means and one or more of said second signals to an output in response to a matrix of programmable interconnections within said second means, wherein said one or more first signals and one or more of said second signals are presented in response to the programming of said programmable interconnections;
- and
- said third means for (i) receiving said one or more first signals from said second means, (ii) presenting said one or more second signals to said matrix of programmable interconnections, and (iii) generating an output frequency in response to said one or more first signals from said second means.
A method for generating an output signal, comprising the steps of:
- (A) generating a plurality of first signals;
- (B) receiving said plurality of first signals and one or more second signals and presenting one or more of said first signals to a first output and one or more of said second signals to a second output in response to a matrix of programmable interconnections, wherein said one or more first signals and said one or more of said second signals are presented in response to the programming of said programmable interconnections;
- and
- (C) receiving said one or more first signals from said first output, presenting said one or more second signals to said matrix of programmable interconnections, and generating said one or more second signals signals from said second output as said output signal in response to said one or more first signals from said first output.
Dependencies are inferred from the claim text.