Output synchronization-free, high-fanin dynamic NOR gate

A NOR gate for evaluating a n-bit word having a selected bit and (n−1) non-selected bits, the NOR gate comprising:

• an output FET;
• a pre-charge circuit for charging a gate, a drain, and a source of said output FET to a pre-charge voltage;
• first evaluation circuit, coupled to said source of said output FET, for evaluating said selected bit;
• (n−1) second evaluation circuits corresponding to said (n−1) non-selected bits, each of said second evaluation circuits being coupled to said gate of said output FET;
• and
• wherein, if said selected bit is a first voltage and each of said (n−1) non-selected bits is a second voltage, then said first evaluation circuit discharges said pre-charge voltage on said source of said output FET, and each of said second evaluation circuits maintains said pre-charge voltage on said gate of said output FET, thereby causing said output FET to conduct and discharge said drain of said output FET, whereby discharging said drain of said output FET indicates an all-zero scenario.

A system for detecting an all-zero scenario for a n-bit word having a selected bit and (n−1) non-selected bits, the system comprising:

• an output FET;
• pre-charging means for pre-charging a gate, a drain, and a source of said output FET;
• first evaluation means for evaluating said selected bit, wherein said first evaluation means discharges said pre-charge voltage on said source of said output FET when said selected bit is a first voltage;
• second evaluation means for evaluating said non-selected bits, wherein said second evaluation means maintains said pre-charge voltage on said gate of said output FET when said (n−1) non-selected bits are a second voltage;
• and
• wherein said output FET conducts when said gate of said output FET is pre-charged and said source of said output FET is discharged, thereby discharging said pre-charge voltage on said drain of said output FET, whereby discharging said output FET drain indicates the all-zero scenario.

A method for detecting a certain value for a n-bit word, the method comprising:

• inverting a selected bit;
• generating a pre-charged voltage;
• evaluating a logic state of the inverted selected bit using a first convention, and a logic state of a non-selected bit using a second convention, said evaluating including:
• (a) determining a voltage of the inverted selected bit, and a voltage of the non-selected bit, and
• (b) discharging the pre-charge voltage if the inverted selected bit is a first voltage, and the non-selected bit is a second voltage, whereby the discharge of the pre-charge voltage indicates the certain value, and
• (c) maintaining the pre-charge voltage if at least one of the following conditions is met
• (I) the inverted selected bit is said second voltage, and
• (ii) at least one of the non-selected bits is said first voltage.

A logic gate, comprising:

• an output FET, a drain of said output FET coupled to an output of said logic gate;
• a pre-charge circuit coupled to a gate, a source, and said drain of said output FET;
• a first evaluation circuit comprising a first FET, a drain of said first FET coupled to said source of said output FET, a source of said first FET coupled to ground, a gate of said first FET coupled to a first input;
• and
• a second evaluation circuit comprising a second FET, a drain of said second FET coupled to said gate of said output FET, a source of said second FET coupled to ground, and a gate of said second FET coupled to a second input.