Method and apparatus for elimination of parasitic bipolar action in logic circuits for history removal under stack contention including complementary oxide semiconductor (CMOS) silicon on insulator (SOI) elements

A method of providing an apparatus with reduced bipolar transistor action including a dynamic logic circuit and a Silicon on Insulator (SOI) Metal Oxide Semiconductor (MOS) device, the method comprising:

• providing a plurality of stacked SOI MOS devices interconnected to perform a predetermined logic function defining a shared node and an intermediate node;
• providing a plurality of series connected active discharging devices defining a discharge path between said intermediate node and a common discharge potential, said plurality of series connected active discharging devices being controlled by respective inputs to said stacked SOI MOS devices;
• and
• arranging said plurality of series connected active discharging devices to selectively discharge said intermediate node to said common discharge potential to eliminate parasitic bipolar transistor action in said stacked SOI MOS devices.

A Silicon on Insulator (SOI) Metal Oxide Semiconductor (MOS) circuit for implementing a logic function, comprising:

• a precharge node precharged by a precharge device;
• an output device coupled to said precharge node;
• a logic network, said logic network selectively discharging said precharge node to a common discharge potential in response to a plurality of inputs to implement a pre-defined logic function, said logic network comprising an intermediate node;
• and
• an active discharge path from said intermediate node to said common discharge potential, said active discharge path selectively discharging said intermediate node to said common discharge potential to prevent parasitic bipolar transistor action.