Semiconductor circuit with sequential circuit which can prevent leakage current
AssigneeNEC Corporation
InventorTadahiko Ogawa
Life of this patent
Estimating the term…
Abstract
A semiconductor circuit includes a logic circuit section and a latch circuit section. The logic circuit section includes higher and lower potential side actual power supply lines, higher and lower potential side quasi power supply lines, a CMOS logic circuit and a power connection section. The latch circuit section includes a first CMOS inverter, a latch circuit and a transfer gate. The first CMOS inverter is connected between the higher and lower potential side quasi power supply lines. The latch circuit is operatively and selectively connected to the first CMOS inverter in series and is composed of second and third CMOS inverters connected in series. The transfer gate has the second threshold voltage and is disposed between the first CMOS inverter and the latch circuit.
Claims32
A semiconductor circuit comprising a logic circuit section and a latch circuit section,
- wherein said logic circuit section includes:
- higher and lower potential side actual power supply lines;
- higher and lower potential side quasi power supply lines;
- a CMOS logic circuit connected between said higher and lower potential side quasi power supply lines and composed of MOS transistors having a first threshold voltage;
- and
- a power connection section which connects at least one of said higher and lower potential side actual power supply lines to a corresponding one of said higher and lower potential side quasi power supply lines, a remaining one of said higher and lower potential side actual power supply lines being directly connected to a corresponding one of said higher and lower potential side quasi power supply lines, wherein said power connection section includes at least one control MOS transistor having a second threshold voltage higher than said first threshold voltage,
- wherein said latch circuit section includes:
- a first CMOS inverter connected between said higher and lower potential side quasi power supply lines;
- a latch circuit operatively and selectively connected to said first CMOS inverter in series and composed of second and third CMOS inverters connected in series;
- and
- a transfer gate having said second threshold voltage and disposed between said first CMOS inverter and said latch circuit.
A sequential circuit comprising:
- higher and lower potential side actual power supply lines;
- higher and lower potential side quasi power supply lines;
- a power connection section which connects at least one of said higher and lower potential side actual power supply lines to a corresponding one of said higher and lower potential side quasi power supply lines, a remaining one of said higher and lower potential side actual power supply lines being directly connected to a corresponding one of said higher and lower potential side quasi power supply lines, wherein said power connection section includes at least one control MOS transistor having a second threshold voltage higher than a first threshold voltage,
- a first CMOS inverter connected between said higher and lower potential side quasi power supply lines, said CMOS inverter including a MOS transistor having said first threshold voltage;
- a latch circuit operatively and selectively connected to said first CMOS inverter in series and composed of second and third CMOS inverters connected in series;
- and
- a transfer gate having said second threshold voltage and disposed between said first CMOS inverter and said latch circuit.
Dependencies are inferred from the claim text.