Input/output circuit with high input/output voltage tolerance

An I/O circuit which operates between a first system voltage and a second system voltage, with the first system voltage being larger than the second system voltage, comprising

• an I/O pad for receiving the first system voltage;
• a transmission gate having an input end connected to the I/O pad and an output end connected to a common node, wherein the transmission gate is composed of a first NMOS transistor and a first PMOS transistor;
• a feedback circuit having an input end connected to the I/O pad and an output end connected to the gate of the first PMOS transistor in the transmission gate;
• a second PMOS transistor whose source is connected to the second system voltage and whose drain is connected to the common node;
• a second NMOS transistor whose source is connected to the ground and whose drain is connected to the common node;
• an input-stage circuit coupled to the I/O pad, the input-stage circuit including:
• a third NMOS transistor, whose source is connected to the I/O pad and whose gate is connected to receive a gate voltage;
• a third PMOS transistor, whose source is connected to the drain of the third NMOS transistor, whose drain is connected to the second system voltage, and whose gate is connected to the first system voltage;
• a fourth PMOS transistor, whose source is connected to the first system voltage, whose drain is connected to the second system voltage, and whose gate is connected to the drain of the third NMOS transistor;
• and a fourth NMOS transistor, whose source is connected to the ground, whose drain is connected to the first system voltage, and whose gate is connected to the drain of the third NMOS transistor;
• wherein
• when the I/O circuit operates in output mode, one of the second PMOS transistor and the second NMOS transistor is switched on, causing the second end of the feedback circuit to be connected to the ground, allowing the I/O pad to achieve full swing;
• when the I/O circuit is put in a high-impedance state while both the second PMOS transistor and the second NMOS transistor are switched off and the first system voltage is smaller than the second system voltage, the voltage at the common node is enabled to track the first system voltage until reaching a magnitude substantially equal to the second system voltage minus the threshold voltage of the first NMOS transistor;
• and
• when the I/O circuit is put in a high-impedance state while both the second PMOS transistor and the second NMOS transistor are switched off and the first system voltage is larger than the second system voltage, the feedback circuit is enabled to cause the first PMOS transistor to be switched off, allowing the voltage at the common node to be maintained at the magnitude equal to the second system voltage minus the threshold voltage of the first NMOS transistor.

An input-stage circuit used in an I/O circuit, coupled between an I/O pad of the I/O circuit and an internal circuit, the I/O pad receiving a first system voltage, the input-stage circuit comprising:

• a third NMOS transistor, a third PMOS transistor, a fourth NMOS transistor, and a fourth PMOS transistor, wherein
• the third NMOS transistor is coupled to the I/O pad from its source electrode, to a gate voltage from its gate, and to a node M from its drain electrode;
• the fourth NMOS transistor is couple to the node M from its gate, to a ground from its source, and to a node N from its drain electrode;
• the third PMOS transistor is coupled to the node N from its drain electrode, to the node M from its gate, and to a second system voltage from its source electrode;
• and
• the fourth PMOS is coupled to the node N from its gate, to the node M from its drain electrode, and to the second system voltage,
• wherein the internal circuit is coupled to the node N.