Microcontroller having a block of logic configurable to perform a selected logic function and to produce output signals coupled to corresponding I/O pads according to a predefined hardware interface

A microcontroller formed upon a single monolithic semiconductor substrate, comprising:

• an internal bus having a plurality of signal lines for conveying signals;
• a CPU configured to execute instructions and to produce a plurality of CPU output signals during instruction execution;
• a first plurality of I/O pads;
• a configurable logic block (CLB) coupled between the internal bus and the first plurality of I/O pads, wherein the CLB is configurable to perform a logic function selected from a predefined set of logic functions, and wherein each member of the predefined set of logic functions has a corresponding hardware interface;
• a second plurality of I/O pads;
• and
• a test/program core coupled to the second plurality of I/O pads and to the CLB, wherein the test/program core is configured to produce programming signals in response to signals received via the second plurality of I/O pads;
• wherein the CLB is configured to perform a selected logic function by the programming signals, and wherein the configured CLB produces a plurality of CLB output signals in response to the plurality of CPU output signals such that each of the plurality of CLB output signals is coupled to one or more of the first plurality of I/O pads according to the hardware interface of the selected logic function.

A microcontroller formed upon a single monolithic semiconductor substrate, comprising:

• an internal bus having a plurality of signal lines for conveying signals;
• a CPU coupled to the internal bus and configured to execute instructions, wherein the CPU produces a plurality of CPU output signals during instruction execution;
• a first plurality of I/O pads;
• a configurable logic block (CLB) coupled between the internal bus and the first plurality of I/O pads, wherein the CLB is configurable to perform a logic function selected from a predefined set of logic functions, and wherein each member of the predefined set of logic functions has a corresponding hardware interface;
• a second plurality of I/O pads;
• a test/program core coupled to the second plurality of I/O pads and to the CLB, wherein the test/program core is configured to produce programming signals in response to signals received via the second plurality of I/O pads;
• a third plurality of I/O pads;
• a memory controller coupled to the internal bus and to the third plurality of I/O pads, wherein the memory controller is configured to control the saving of data within and the retrieving of data from one or more memory devices coupled to the third plurality of I/O pads;
• a fourth plurality of I/O pads;
• and
• an expansion bus interface coupled to the internal bus and to the fourth plurality of I/O pads, wherein the expansion bus interface is configured to control an expansion bus coupled to the fourth plurality of I/O pads;
• wherein the CLB is configured to perform a selected logic function by the programming signals, and wherein the configured CLB produces a plurality of CLB output signals in response to the plurality of CPU output signals such that each of the plurality of CLB output signals is coupled to one or more of the first plurality of I/O pads according to the hardware interface of the selected logic function.

A microcontroller, comprising:

• a CPU configured to execute instructions and to produce a plurality of CPU output signals during instruction execution;
• a plurality of I/O pads;
• a configurable logic block (CLB) coupled to receive the plurality of CPU output signals and coupled to the first plurality of I/O pads, wherein the CLB is configurable to perform a logic function selected from a predefined set of logic functions, and wherein each member of the predefined set of logic functions has a corresponding hardware interface;
• and
• programming hardware coupled to the CLB for configuring the CLB to perform the selected logic function.

A microcontroller, comprising:

• a CPU configured to execute instructions and to produce a plurality of CPU output signals during instruction execution;
• a first plurality of I/O pads;
• a configurable logic block (CLB) coupled to receive the plurality of CPU output signals and coupled to the first plurality of I/O pads, wherein the CLB is configurable to perform a logic function selected from a predefined set of logic functions, and wherein each member of the predefined set of logic functions has a corresponding hardware interface;
• a second plurality of I/O pads;
• and
• programming hardware coupled to the second plurality of I/O pads and to the CLB, wherein the programming hardware is configured to produce programming signals in response to signals received via the second plurality of I/O pads, and wherein the programming signals configure the CLB to perform the selected logic function.