Programmable function block

A programmable core logic circuit comprising:

• a core logic circuit (4, 4A, 4B, 4C) having a first argument input group consisting of first through fourth argument input terminals (A0, A1, A2, A3), a second argument input group consisting of first though fourth argument input terminals (B0, B1, B2, B3), first through third configuration input terminals (M0, M1, M2), a core logic carry output terminal (C) for outputting a core logic carry output signal, a core logic carry generation output terminal (GO) for outputting a core logic carry generation output signal, a core logic carry propagation output terminal (PO) for outputting a core logic carry propagation output signal, a ripple-core logic carry input terminal (CCI) for inputting a ripple-core logic carry input signal, and a sum output terminal (S) for outputting a summed output signal;
• and
• an input block (3) connected to said core logic circuit and to interconnecting wires (8), said input block including first through fourth input selection units (3.A0, 3.A1, 3.A2, 3.A3) connected to the first through the fourth argument input terminals (A0, A1, A2, A3) in said first argument input group, respectively, and fifth through eighth input selection units (3.B0, 3.B1, 3.B2, 3.B3) connected to the first through the fourth argument input terminals (B0, B1, B2, B3) in said second argument input group, said first through said fourth input selection units selecting, as first through fourth input selected signals, one of signals on said interconnecting wires, a fixed logic value of “1”, and a fixed logic value of “0” to supply the first through the fourth input selected signals to the first through the fourth argument input terminals (A0, A1, A2, A3) in said first argument input group, respectively, said fifth through eighth input selection units selecting, as fifth through eighth input selected signals, one of signals on said interconnecting wires, the fixed logic value of “1”, and the fixed logic value of “0” to supply the fifth through the eighth input selected signals to the first through the fourth argument input terminals (B0, B1, B2, B3) in said second argument input group, respectively.

A logic block comprising:

• a core logic circuit (4, 4A, 4B, 4C) having a first argument input group consisting of first through fourth argument input terminals (A0, A1, A2, A3), a second argument input group consisting of first though fourth argument input terminals (B0, B1, B2, B3), first through third configuration input terminals (M0, M1, M2), a core logic carry output terminal (C) for outputting a core logic carry output signal, a core logic carry generation output terminal (GO) for outputting a core logic carry generation output signal, a core logic carry propagation output terminal (PO) for outputting a core logic carry propagation output signal, a ripple-core logic carry input terminal (CCI) for inputting a ripple-core logic carry input signal, and a sum output terminal (S) for outputting a summed output signal;
• first through third memory circuits (6.0, 6.1, 6.2) connected to said first through said third configuration input terminals (M0, M1, M2), respectively, said first through said third memory circuits storing a logic value of one bit as first through third stored signals, said first through said third memory circuits supplying the first through the third stored signals to said first through said third configuration input terminals, respectively;
• and
• a carry logic circuit (5, 5A) having a ripple carry input terminal (RCI) for inputting a ripple carry input signal, a ripple carry output terminal (RCO) for outputting a ripple carry output signal, a ripple-core logic carry output terminal (CCO) for supplying said ripple-core logic carry input terminal (CCI) with a ripple-core logic carry output signal as the ripple-core logic carry input signal, a core logic carry generation input terminal (G) for being supplied from said core logic carry generation output terminal (GO) with the core logic carry generation output signal as a core logic carry generation input signal, and a core logic carry propagation input terminal (P) for being supplied from said core logic carry propagation output terminal (PO) with the core logic carry propagation output signal as a core logic carry propagation input signal.

A Function device comprising a plurality of logic blocks, each of said logic blocks comprising:

• a core logic circuit (4, 4A, 4B, 4C) having a first argument input group consisting of first through fourth argument input terminals (A0, A1, A2, A3), a second argument input group consisting of first though fourth argument input terminals (B0, B1, B2, B3), first through third configuration input terminals (M0, M1, M2), a core logic carry output terminal (C) for outputting a core logic carry output signal, a core logic carry generation output terminal (GO) for outputting a core logic carry generation output signal, a core logic carry propagation output terminal (PO) for outputting a core logic carry propagation output signal, a ripple-core logic carry input terminal (CCI) for inputting a ripple-core logic carry input signal, and a sum output terminal (S) for outputting a summed output signal;
• first through third memory circuits (6.0, 6.1, 6.2) connected to said first through said third configuration input terminals (M0, M1, M2), respectively, said first through said third memory circuits storing, as first through third stored signals, a logic value of one bit, said first through said third memory circuits supplying the first through the third stored signals to said first through said third configuration input terminals, respectively;
• and
• a carry logic circuit (5, 5A) having a ripple carry input terminal (RCI) for inputting a ripple carry input signal, a ripple carry output terminal (RCO) for outputting a ripple carry output signal, a ripple-core logic carry output terminal (CCO) for supplying said ripple-core logic carry input terminal (CCI) with a ripple-core logic carry output signal as the ripple-core logic carry input signal, a core logic carry generation input terminal (G) for being supplied from said core logic carry generation output terminal (GO) with the core logic carry generation output signal as a core logic carry generation input signal, and a core logic carry propagation input terminal (P) for being supplied from said core logic carry propagation output terminal (PO) with the core logic carry propagation output signal as a core logic carry propagation input signal,
• said ripple carry output terminal (RCO) of at least one of said logic blocks being connected to the ripple carry input terminal (RCI) of another one of said logic blocks.

A function device comprising at least one odd logic block and at least one even logic block which are alternately arranged,

• said odd logic block comprising:
• a first core logic circuit (41) having a first argument input group consisting of first through fourth argument input terminals (A01, A11, A21, A31), a second argument input group consisting of first though fourth argument input terminals (B01, B11, B21, B31), first through third configuration input terminals (M01, M11, M21), a first core logic carry output terminal (C1) for outputting a first core logic carry output signal, a first core logic carry generation output terminal (GO1) for outputting a first core logic carry generation output signal, a first core logic carry propagation output terminal (PO1) for outputting a first core logic carry propagation output signal, a first ripple-core logic carry input terminal (CCI1) for inputting a first ripple-core logic carry input signal, and a first sum output terminal (S1) for outputting a first summed output signal;
• first through third memory circuits connected to said first through said third configuration input terminals (M01, M11, M21), respectively, each of said first through said third memory circuits storing a logic value of one bit, said first through said third memory circuits supplying first through third stored signals to said first through said third configuration input terminals, respectively;
• and
• an odd carry logic circuit (5.1) having a ripple carry input terminal (RCI) for inputting a ripple carry input signal from a ripple carry propagation path (7), a ripple carry inverted output terminal (RCOb) for outputting a ripple carry inverted output signal to said ripple carry propagation path (7), a first ripple-core logic carry output terminal (CCO1) for supplying said first ripple-core logic carry input terminal (CCI1) with a first ripple-core logic carry output signal as the first ripple-core logic carry input signal, a first core logic carry generation input terminal (G1) for being supplied from said first core logic carry generation output terminal (GO1) with the first core logic carry generation output signal as a first core logic carry generation input signal, and a first core logic carry propagation input terminal (P1) for being supplied from said first core logic carry propagation output terminal (PO) with the first core logic carry propagation output signal as a first core logic carry propagation input signal,
• said even logic block comprising:
• a second core logic circuit (42) having a third argument input group consisting of first through fourth argument input terminals (A02, A12, A22, A32), a fourth argument input group consisting of first though fourth argument input terminals (B02, B12, B22, B32), fourth through sixth configuration input terminals (M02, M12, M22), a second core logic carry output terminal (C2) for outputting a second core logic carry output signal, a second core logic carry generation output terminal (G02) for outputting a second core logic carry generation output signal, a second core logic carry propagation output terminal (P02) for outputting a second core logic carry propagation output signal, a second ripple-core logic carry input terminal (CCI2) for inputting a second ripple-core logic carry input signal, and a second sum output terminal (S2) for outputting a second summed output signal;
• fourth through sixth memory circuits connected to said fourth through said sixth configuration input terminals (M02, M12, M22), respectively, each of said fourth through said sixth memory circuits storing a logic value of one bit, said fourth through said sixth memory circuits supplying fourth through sixth stored signals to said fourth through said sixth configuration input terminals, respectively;
• and
• an even carry logic circuit (5.2) having a ripple carry inverted input terminal (RCIb) for inputting a ripple carry inverted input signal from said ripple carry propagation path (7), a ripple carry output terminal (RCO) for outputting a ripple carry output signal to said ripple carry propagation path (7), a second ripple-core logic carry output terminal (CCO2) for supplying said second ripple-core logic carry input terminal (CCI2) with a second ripple-core logic carry output signal as the second ripple-core logic carry input signal, a second core logic carry generation input terminal (G2) for being supplied from said second core logic carry generation output terminal (G02) with the second core logic carry generation output signal as a second core logic carry generation input signal, and a second core logic carry propagation input terminal (P2) for being supplied from said second core logic carry propagation output terminal (PO2) with the second core logic carry propagation output signal as a second core logic carry propagation input signal.

A programmable function block comprising:

• a core logic circuit (4, 4A, 4B, 4C) having a first argument input group consisting of first through fourth argument input terminals (A0, A1, A2, A4), a second argument input group consisting of first through fourth argument input terminals (B0, B1, B2, B3), first through third configuration input terminals (M0, M1, M2), a core logic carry output terminal (C) for outputting a core logic carry output signal, a core logic carry generation output terminal (GO) for outputting a core logic carry generation output signal, a core logic carry propagation output terminal (PO) for outputting a core logic carry propagation output signal, a ripple-core logic carry input terminal (CCI) for inputting a ripple-core logic carry input terminal, and a sum output terminal (S) for outputting a summed output signal;
• an input block (3) connected to interconnection wires and the first and the second argument input groups, said input block including eighth input selection units for selecting, as eight input selected signals, eight ones of signals on the interconnection wires, a fixed logic value of “1”, and a fixed logic value of “0”, said input selection units supplying the eight input selected signals to said first through said fourth argument input terminals of the first and the second argument input groups;
• first through third memory circuits (6.0, 6.1, 6.3), connected to the first through the third configuration input terminals (M0, M1, M2), respectively, for storing, as first through third stored logic values, a logic value of one bit, said first through said third memory circuits supplying the first through the third stored logic values to the first through the third configuration input terminals, respectively;
• and
• a carry logic circuit (5, 5A) having a ripple carry input terminal (RCI) for inputting a ripple carry input signal from a ripple carry propagation path (7), a ripple carry output terminal (RCO) for outputting a ripple carry output signal to said ripple carry propagation path (7), a ripple-core logic carry output terminal (CCO) for supplying the ripple-core logic carry input terminal (CCI) with a ripple-core logic carry output signal as the ripple-core logic carry input signal, a core logic carry generation input terminal (G) for inputting the core logic carry generation output signal as a core logic carry generation input signal from the core logic carry output terminal (GO), and a core logic carry propagation input terminal (P) for inputting the core logic carry propagation output signal as a core logic carry propagation input signal from the core logic carry propagation output terminal (PO).

A programmable function device comprising a plurality of programmable function blocks, each of said programmable function blocks comprising:

• a core logic circuit (4, 4A, 4B, 4C) having a first argument input group consisting of first through fourth argument input terminals (A0, A1, A2, A4), a second argument input group consisting of first through fourth argument input terminals (B0, B1, B2, B3), first through third configuration input terminals (M0, M1, M2), a core logic carry output terminal (C) for outputting a core logic carry output signal, a core logic carry generation output terminal (GO) for outputting a core logic carry generation output signal, a core logic carry propagation output terminal (PO) for outputting a core logic carry propagation output signal, a ripple-core logic carry input terminal (CCI) for inputting a ripple-core logic carry input terminal, and a sum output terminal (S) for outputting a summed output signal;
• an input block (3) connected to interconnection wires and the first and the second argument input groups, said input block including eighth input selection units for selecting, as eight input selected signals, eight ones of signals on the interconnection wires, a fixed logic value of “1”, and a fixed logic value of “0”, said input selection units supplying the eight input selected signals to said first through said fourth argument input terminals of the first and the second argument input groups;
• first through third memory circuits (6.0, 6.1, 6.3), connected to the first through the third configuration input terminals (M0, M1, M2), respectively, for storing, as first through third stored logic values, a logic value of one bit, said first through said third memory circuits supplying the first through the third stored logic values to the first through the third configuration input terminals, respectively;
• and
• a carry logic circuit (5, 5A) having a ripple carry input terminal (RCI) for inputting a ripple carry input signal from a ripple carry propagation path (7), a ripple carry output terminal (RCO) for outputting a ripple carry output signal to said ripple carry propagation path (7), a ripple-core logic carry output terminal (CCO) for supplying the ripple-core logic carry input terminal (CCI) with a ripple-core logic carry output signal as the ripple-core logic carry input signal, a core logic carry generation input terminal (G) for inputting the core logic carry generation output signal as a core logic carry generation input signal from the core logic carry output terminal (GO), and a core logic carry propagation input terminal (P) for inputting the core logic carry propagation output signal as a core logic carry propagation input signal from the core logic carry propagation output terminal (PO),
• said ripple carry output terminal (RCO) of at least one of said programmable function blocks being connected to the ripple carry input terminal (RCI) of another one of said programmable function blocks.

A programmable function device comprising at least one odd programmable function block (1.1) and at least one even programmable function block (1.2) which are alternately arranged,

• said odd programmable function block (1.1) comprising:
• a first core logic circuit (41) having a first argument input group consisting of first through fourth argument input terminals (A01, All, A21, A31), a second argument input group consisting of first though fourth argument input terminals (B01, B1, B21, B31), first through third configuration input terminals (M01, M11, M21), a first core logic carry output terminal (C1) for outputting a first core logic carry output signal, a first core logic carry generation output terminal (GO1) for outputting a first core logic carry generation output signal, a first core logic carry propagation output terminal (PO1) for outputting a first core logic carry propagation output signal, a first ripple-core logic carry input terminal (CCI1) for inputting a first ripple-core logic carry input signal, and a first sum output terminal (SI) for outputting a first summed output signal;
• a first input block circuit (31) connected to interconnecting wires and said first and said second argument input groups of said first core logic circuit (41), said first input block circuit comprising eight input selection units for selecting eight input selected signals from signals on said interconnecting wires, a fixed logic value of “1”, and a fixed logic value of “0” to supply the eight input selected signals to the first through the fourth argument input terminals of said first and said second argument input groups in said first core logic circuit;
• first through third memory circuits connected to said first through said third configuration input terminals (M01, M11, M21), respectively, said first through said third memory circuits storing, as first through third stored signals, a logic value of one bit, said first through said third memory circuits supplying the first through the third stored signals to said first through said third configuration input terminals, respectively;
• and
• an odd carry logic circuit (5.1) having a ripple carry input terminal (RCI) for inputting a ripple carry input signal from a ripple carry propagation path (7), a ripple carry inverted output terminal (RCOb) for outputting a ripple carry inverted output signal to said ripple carry propagation path (7), a first ripple-core logic carry output terminal (CCO1) for supplying said first ripple-core logic carry input terminal (CCI1) with a first ripple-core logic carry output signal as the first ripple-core logic carry input signal, a first core logic carry generation input terminal (G1) for being supplied from said first core logic carry generation output terminal (GO1) with the first core logic carry generation output signal as a first core logic carry generation input signal, and a first core logic carry propagation input terminal (P1) for being supplied from said first core logic carry propagation output terminal (PO1) with the first core logic carry propagation output signal as a first core logic carry propagation input signal,
• said even programmable function block (1.2) comprising:
• a second core logic circuit (42) having a third argument input group consisting of first through fourth argument input terminals (A02, A12, A22, A32), a fourth argument input group consisting of first though fourth argument input terminals (B02, B12, B22, B32), fourth through sixth configuration input terminals (M02, M12, M22), a second core logic carry output terminal (C2) for outputting a second core logic carry output signal, a second core logic carry generation output terminal (GO2) for outputting a second core logic carry generation output signal, a second core logic carry propagation output terminal (PO2) for outputting a second core logic carry propagation output signal, a second ripple-core logic carry input terminal (CCI2) for inputting a second ripple-core logic carry input signal, and a second sum output terminal (S2) for outputting a second summed output signal;
• a second input block circuit (32) connected to interconnecting wires and said third and said fourth argument input groups of said second core logic circuit (42), said second input block circuit comprising eight input selection units for selecting eight input selected signals from signals on said interconnecting wires, a fixed logic value of “1”, and a fixed logic value of “0” to supply the eight input selected signals to the first through the fourth argument input terminals of said third and said fourth argument input groups in said second core logic circuit;
• fourth through sixth memory circuits connected to said fourth through said sixth configuration input terminals (M02, M12, M22), respectively, each of said fourth through said sixth memory circuits storing a logic value of one bit, said fourth through said sixth memory circuits supplying fourth through sixth stored signals to said fourth through said sixth configuration input terminals, respectively;
• and
• an even carry logic circuit (5.2) having a ripple carry inverted input terminal (RCIb) for inputting a ripple carry inverted input signal from said ripple carry propagation path (7), a ripple carry output terminal (RCO) for outputting a ripple carry output signal to said ripple carry propagation path (7), a second ripple-core logic carry output terminal (CCO2) for supplying said second ripple-core logic carry input terminal (CCI2) with a second ripple-core logic carry output signal as the second ripple-core logic carry input signal, a second core logic carry generation input terminal (G2) for being supplied from said second core logic carry generation output terminal (GO2) with the second core logic carry generation output signal as a second core logic carry generation input signal, and a second core logic carry propagation input terminal (P2) for being supplied from said second core logic carry propagation output terminal (PO2) with the second core logic carry propagation output signal as a second core logic carry propagation input signal.

A programmable function module comprising:

• a programmable function block comprising a core logic circuit (4, 4A, 4B, 4C) having a first argument input group consisting of first through fourth argument input terminals (A0, A1, A2, A4), a second argument input group consisting of first through fourth argument input terminals (B0, B1, B2, B3), first through third configuration input terminals (M0, M1, M2), a core logic carry output terminal (C) for outputting a core logic carry output signal, a core logic carry generation output terminal (GO) for outputting a core logic carry generation output signal, a core logic carry propagation output terminal (PO) for outputting a core logic carry propagation output signal, a ripple-core logic carry input terminal (CCI) for inputting a ripple-core logic carry input terminal, and a sum output terminal (S) for outputting a summed output signal, an input block (3) connected to interconnection wires and the first and the second argument input groups, said input block including eighth input selection units for selecting, as eight input selected signals, eight ones of signals on the interconnection wires, a fixed logic value of “1”, and a fixed logic value of “0”, said input selection units supplying the eight input selected signals to said first through said fourth argument input terminals of the first and the second argument input groups, first through third memory circuits (6.0, 6.1, 6.3), connected to the first through the third configuration input terminals (M0, M1, M2), respectively, for storing, as first through third stored logic values, a logic value of one bit, said first through said third memory circuits supplying the first through the third stored logic values to the first through the third configuration input terminals, respectively, and a carry logic circuit (5, 5A) having a ripple carry input terminal (RCI) for inputting a ripple carry input signal from a ripple carry propagation path (7), a ripple carry output terminal (RCO) for outputting a ripple carry output signal to said ripple carry propagation path (7), a ripple-core logic carry output terminal (CCO) for supplying the ripple-core logic carry input terminal (CCI) with a ripple-core logic carry output signal as the ripple-core logic carry input signal, a core logic carry generation input terminal (G) for inputting the core logic carry generation output signal as a core logic carry generation input signal from the core logic carry output terminal (GO), and a core logic carry propagation input terminal (P) for inputting the core logic carry propagation output signal as a core logic carry propagation input signal from the core logic carry propagation output terminal (PO);
• a first register block (41.0) having a first date input terminal (D11) connected to said sum output terminal (S), a first clock input terminal (CLK1) supplied with a clock signal, a first clock enable input terminal (E1) supplied with a first clock enable signal, a first set/reset input terminal (SRI) supplied with a first set/reset input signal, a fourth configuration input terminal (M31), and a first data output terminal (DO1);
• a second register block (41.1) having a second date input terminal (D12) connected to said core logic carry output terminal (C), a second clock input terminal (CLK2) supplied with the clock signal, a second clock enable input terminal (E2) supplied with a second clock enable signal, a second set/reset input terminal (SR2) supplied with a second set/reset input signal, a fifth configuration input terminal (M32), and a second data output terminal (DO1);
• a fourth memory circuit (6.80) connected to said fourth configuration input terminal (M31);
• a fifth memory circuit (6.81) connected to said fifth configuration input terminal (M32);
• a first clock enable input selection circuit (3.E0), connected to said interconnecting wires (8) and said first clock enable input terminal (E1), for supplying the first clock enable signal to said first clock enable input terminal (E1);
• a second clock enable input selection circuit (3.E1), connected to said interconnecting wires (8) and said second clock enable input terminal (E2), for supplying the second clock enable signal to said second clock enable input terminal (E2);
• a first set/reset input selection circuit (3.SR0), connected to said interconnecting wires (8) and said first set/reset input terminal (SR1), for the first set/reset input signal to said first set/reset input terminal (SR1);
• a second set/reset input selection circuit (3.SR1), connected to said interconnecting wires (8) and said second set/reset input terminal (SR2), for the second set/reset input signal to said second set/reset input terminal (SR2);
• a first output unit (42.0), connected to said first data output terminal (DO1) and said interconnecting wires (8), for supplying a first data output signal from said first data output terminal (DO1) to said interconnecting wires (8);
• and
• a second output unit (42.1), connected to said second data output terminal (DO2) and said interconnecting wires (8), for supplying a second data output signal from said second data output terminal (DO2) to said interconnecting wires (8).