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US 6,188,237 B1Granted
Impedance matching circuit, high speed semiconductor integrated circuit employing the same and computer system employing the integrated circuit
AssigneeKabushiki Kaisha Toshiba
InventorsAzuma Suzuki, Shigeyuki Hayakawa
Life of this patent
Estimating the term…
Abstract
A high speed impedance matching circuit suitable for use in high speed semiconductor integrated circuits matches the output impedance of a semiconductor device to the impedance of other devices such a computer system bus thereby reducing signal reflections caused by impedance mismatches and which can adversely affect the operation of a high speed computer system. The impedance of an output buffer is matched to the impedance of an external resistor.
Claims22
An impedance matching circuit connected between an output buffer and a specific terminal disposed on a semiconductor chip for connecting an external resistor, comprising:
- (a) an external resistance monitoring circuit having:
- a generator for generating a reference potential;
- a potential controller for fixing a potential of the specific terminal at the reference potential;
- a detector for detecting a current passing through the external resistor;
- and
- a matching controller for matching an impedance of the output buffer with an impedance of the external resistor determined according to a current detected by the detector, or an inverse multiple of the impedance of the external resistor;
- and
- (b) a dummy buffer connected to the matching controller and made of transistors connected in parallel.
5 more elements
An impedance matching circuit connected to pull-down and pull-up output buffers and to a specific terminal disposed on a semiconductor chip for connecting an external resistor, comprising:
- (a) an external resistance monitoring circuit having:
- a generator for generating a reference potential;
- a potential controller for fixing a potential of the specific terminal at the reference potential;
- a detector for detecting a current passing through the external resistor;
- a pull-down matching controller for matching an impedance of the pull-down output buffer with a pull-down impedance of the external resistor determined according to a current detected by the detector, or an inverse multiple of the pull-down impedance of the external resistor;
- and
- a pull-up matching controller for matching an impedance of the pull-up output buffer with an pull-up impedance of the external resistor determined according to a current flowing to the detector, or an inverse multiple of the pull-up impedance of the external resistor;
- (b) a pull-up dummy buffer connected to the pull-up matching controller and pull-up output buffer and made of transistors connected in parallel;
- and
- (c) a pull-down dummy buffer connected to the pull-down matching controller and pull-down output buffer and made of transistors connected in parallel.
7 more elements
A semiconductor integrated circuit comprising:
- (a) a semiconductor chip;
- (b) an internal circuit disposed on the semiconductor chip;
- (c) peripheral circuits for driving the internal circuit;
- (d) a specific terminal disposed on the semiconductor chip for connecting an external resistor;
- (e) an output buffer connected to the peripheral circuits;
- (f) an external resistance monitoring circuit connected to the specific terminal, having:
- a generator for generating a reference potential;
- a potential controller for fixing the potential of the specific terminal at the reference potential;
- a detector for detecting a current passing through the external resistor;
- and
- a matching controller for matching an impedance of the output buffer with a impedance of the external resistor determined according to a current detected by the detector, or an inverse multiple of the impedance of the external resistor;
- (g) a dummy buffer connected between the external resistance monitoring circuit and the output buffer and made of transistors connected in parallel;
- and
- (h) an input/output terminal connected to the output buffer.
11 more elements
A computer system comprising:
- (a) a first system bus;
- (b) a second system bus held at low level supply voltage;
- (c) an external resistor connected to the second system bus;
- and
- (d) a semiconductor integrated circuit having:
- a semiconductor chip;
- an internal circuit disposed on the semiconductor chip;
- peripheral circuits for driving the internal circuit;
- a specific terminal disposed on the semiconductor chip for connecting the external resistor;
- an output buffer connected to the peripheral circuits;
- an external resistance monitoring circuit connected to the specific terminal, having:
- a generator for generating a reference potential;
- a potential controller for fixing the potential of the specific terminal at the reference potential;
- a detector for detecting a current passing through the external resistor;
- and
- a matching controller for matching an impedance of the output buffer with an impedance of the external resistor determined according to a current detected by the detector, or an inverse multiple of the impedance of the external resistor;
- a dummy buffer connected between the external resistance monitoring circuit and the output buffer and made of transistors connected in parallel;
- and
- an input/output terminal connected between the output buffer and the first system bus.
16 more elements
Dependencies are inferred from the claim text.