Method of determining dielectric time-to-breakdown
AssigneeInternational Business Machines Corporation
InventorsWagdi W. Abadeer, Jonathan M. McKenna
Life of this patent
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Abstract
A method of determining time-to-breakdown of a gate dielectric in an NFET or a PFET transistor. For an NFET transistor, the method includes providing an N+ injector ring in the p-substrate and forward biasing the N+ injector ring with respect to the p-substrate. A first positive reference voltage level is applied to the source and the drain regions. A second positive reference voltage level is applied to the gate dielectric. The first and second positive reference voltage levels are maintained on the transistor until breakdown of the gate dielectric occurs. Another embodiment of the method may be used in a PFET transistor.
Claims18
A method of determining time-to-breakdown of a gate dielectric in an NFET transistor, the method comprising the steps of:
- (a) providing an N+ injector ring in a p-substrate of the transistor,
- (b) forward biasing the N+ injector ring with respect to the p-substrate,
- (c) applying a first positive reference voltage level to a source region and a drain region of the transistor,
- (d) applying a second positive reference voltage level to the gate dielectric, the second positive reference voltage level higher than the first positive reference voltage level, and
- (e) maintaining the first and second positive reference voltage levels until breakdown of the gate dielectric occurs.
A method of determining time-to-breakdown of a gate dielectric in a PFET transistor, the method comprising the steps of:
- (a) providing an P+ injector ring in an N-well region of the transistor,
- (b) forward biasing the P+ injector ring with respect to an N-well of the transistor,
- (c) applying a first negative reference voltage level to a source region and a drain region of the transistor,
- (d) applying a second negative reference voltage level to the gate dielectric, the second negative reference voltage level having a higher absolute magnitude than the first negative reference voltage level, and
- (e) maintaining the first and second negative reference voltage levels until breakdown of the gate dielectric occurs.
Dependencies are inferred from the claim text.