High impedance load for integrated circuit devices
AssigneeSTMicroelectronics S.r.l.
InventorFrank Randolph Bryant
Life of this patent
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Abstract
A high impedance load for an integrated circuit device provides an undoped, or lightly doped, layer of epitaxial silicon. The epitaxial silicon layer is formed over a conductive region in a substrate, such as a source/drain region. A highly conductive contact, such as a refractory metal silicide interconnect layer, is formed on top of the epitaxial silicon layer. Preferably, the epitaxial silicon layer is formed using solid phase epitaxy, from excess silicon in the silicide layer, by annealing the device after the silicide layer has been deposited.
Claims24
A high impedance load device in an integrated circuit comprising:
- an opening in an insulating layer exposing a first layer;
- a plug of a refractory metal silicide located in the opening;
- and
- a layer of very low conductivity epitaxial silicon separating the plug and the first layer to provide a high impedance region, wherein the epitaxial silicon results from annealing the integrated circuit.
A static random access memory in an integrated circuit comprising:
- a pass gate transistor;
- a pull-down transistor, the pull-down transistor shares a source/drain region with the pass gate transistor;
- an insulating layer covering the two transistors;
- an opening in the insulating layer over the shared source/drain region;
- a region of a refractory metal silicide in the opening;
- and
- an epitaxial silicon layer deposited from the refractory metal silicide between the region of refractory metal silicide and the source/drain region, wherein the epitaxial silicon layer results from annealing the integrated device.
Dependencies are inferred from the claim text.