High density MOS-gated power device and process for forming same

Abstract

A high density MOS-gated device comprises a semiconductor substrate and a doped upper layer of a first conduction type disposed on the substrate. The upper layer comprises a heavily doped source region of the first conduction type and a doped well region of a second and opposite conduction type at an upper surface. The upper surface, which comprises a contact area for the source region, further includes a recessed portion that comprises a contact area for a heavily doped deep body region of the second conduction type in the upper layer underlying the recessed portion. The device further includes a trench gate disposed in the upper layer and comprising a conductive material separated from the upper layer by an insulating layer. A process for forming a high density MOS-gated device comprises providing a semiconductor substrate comprising a doped upper layer of a first conduction type. A doped well region of a second and opposite conduction type is formed in an upper surface of the upper layer, and a dopant of the first conduction type is implanted in the well region to form a heavily doped source region. A layer of nitride is formed on the upper surface of the upper layer, and the nitride layer and upper layer are selectively etched, thereby forming a trench in the upper layer. The trench is lined with an insulating layer, then filled with a conductive material to form a trench gate. The nitride layer is removed, and a layer of interlevel dielectric material is formed on the trench gate and the upper surface of the upper layer. The interlevel dielectric layer is selectively etched, thereby forming a source region contact area. The source region is selectively etched to form a shallow recess that provides a body region contact area. A dopant of the second conduction type is implanted into the recess, thereby forming a deep body region underlying the recess.

Dependencies are inferred from the claim text.