US 6,188,090 B1Granted

Semiconductor device having a heteroepitaxial substrate

AssigneeFujitsu Limited

InventorsShinji Miyagaki, Takashi Eshita, Satoshi Ohkubo, Kazuaki Takai

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Abstract

A method for fabricating a compound semiconductor device includes the steps of depositing a first group III-V compound semiconductor layer on a surface of a Si substrate while holding a temperature of the Si substrate at a first temperature, depositing a second group III-V compound semiconductor layer on the first group III-V compound semiconductor layer while holding the temperature of the substrate at a second, higher temperature, and depositing a third group III-V compound semiconductor layer on the second group III-V compound semiconductor layer while holding the temperature of the substrate at a third temperature higher than said second temperature, wherein the second group III-V compound semiconductor layer contains Al.

Claims12

Dependent claims

A compound semiconductor device, comprising:

a Si substrate;
a first group III-V compound semiconductor layer provided on said Si substrate, said first group III-V compound semiconductor layer having a thickness set to enable a direct deposition of said first group III-V compound semiconductor layer on a surface of said Si substrate, said Si substrate containing oxidation-induced stacking faults with a density sufficient for suppressing a diffusion of a group V element in said first group III-V compound semiconductor layer into said Si substrate;
a second group III-V compound semiconductor layer provided on said first group III-V compound semiconductor layer, said second group III-V compound semiconductor layer containing Al and having a thickness that minimizes a surface roughness thereof;
a third group III-V compound semiconductor layer provided on said second group III-V compound semiconductor layer;
a fourth group III-V compound semiconductor layer provided on said third group III-V compound semiconductor layer;
and
an active device formed on said fourth group III-V compound semiconductor layer.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/026,915Filed 20 Feb 1998 · division
Priority: 31 Aug 1995
Granted: 13 Feb 2001
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10P 14/2905
Being Group IVA materials: silicon, silicon germanium or germanium
H10D 30/015
Manufacture or treatment: of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
H10P 14/24
Of semiconductor materials: using chemical vapour deposition [CVD]
H10P 14/2926
Characterised by the substrates: crystal orientations

Family

Application08/520,939Parent of this continuation-in-part · filed 31 Aug 1995
Application08/619,249Parent of this division · filed 21 Mar 1996
US 5,834,362 AParent of this division
Application08/619,249Parent of this continuation-in-part
US 6,188,090 B1This patent

From the US filing history. Foreign family members aren’t listed.