Method for final passivation of integrated circuit
AssigneeSGS-Thomson Microelectronics S.A.
InventorsGiorgio De Santi, Luca Zanotti, Giuseppe Crisenza
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Abstract
A planarization method is disclosed to provide improved protection against cracking of the final passivation layer of integrated circuit devices. In one embodiment, such method includes final passivation of an integrated circuit device including at least one integrated circuit chip. Such final passivation includes the step of forming a layer of protective material over a top surface of the integrated circuit chip, and a subsequent step of planarizing such layer of protective material to obtain a protection layer having a substantially flat top surface.
Claims14
A process of final passivation of an integrated circuit device comprising at least one chip, said process comprising the steps of:
- forming a final passivation layer over a top surface of said at least one chip, said forming step comprising a High-Density Plasma Chemical Vapor Deposition (HDPCVD) of a protective material;
- and
- planarizing a top surface of said final passivation layer;
- said planarization step comprising one of a chemical mechanical polishing (CMP) and a reactive ion etching (RIE) of said top surface of said final passivation layer.
Dependencies are inferred from the claim text.