Node process integration technology to improve data retention for logic based embedded dram

A method for forming contact nodes in semiconductor devices, said contact nodes having a lower layer and an upper layer, comprising the steps of:

• providing a semiconductor substrate;
• creating partially completed logic based embedded DRAM structures on the surface of said substrate said partially completed DRAM structures to contain gate electrodes with gate spacers and gate source and drain regions with gate and source/drain regions contact openings;
• depositing a layer of insulation material over said partially completed logic based embedded DRAM structures, including said contact openings;
• patterning and etching said layer of insulation material, creating openings in said layer of insulation material that align with said contact openings;
• depositing a layer of heavily doped polysilicon over said layer of insulation material thereby including said contact openings;
• depositing a layer of lightly doped polysilicon over said layer of heavily doped polysilicon;
• performing a Rapid Thermal Anneal to said heavily and said lightly doped layers of polysilicon in a nitric or inert gas atmosphere at a temperature between about 700 and 750 degrees C. for a period between about 30 seconds and 2 minutes or by furnace exposure;
• removing said lightly doped layer of polysilicon, partially removing said heavily doped layer of polysilicon, creating said lower layer of said contact node, creating a plane of intersection between said lower layer and said upper layer of said contact node;
• depositing a layer of lightly doped polysilicon over said plane of intersection between said lower layer and said upper layer of said contact node;
• and
• patterning said lightly doped polysilicon to form said upper layer of said contact node said upper layer of said contact node to align with said lower layer of said contact node.

A method for fabricating a logic based embedded DRAM on the surface of a semiconductor substrate, forming conductive plugs containing an upper and lower section to provide electrical contact between an active region in said semiconductor substrate and interconnection metalization, comprising the steps of:

• providing partially completed DRAM devices on the surface of said substrate said partially completed DRAM devices having openings for said conductive plugs;
• providing said active region in said partially completed DRAM devices;
• depositing a first layer of polysilicon on said layer of insulation including said openings for said conductive plugs;
• depositing a second layer of polysilicon over said first layer of polysilicon;
• performing a Rapid Thermal Anneal of said first and said second layer of polysilicon;
• removing said second layer of polysilicon thereby partially removing said first layer of polysilicon thereby creating an interface thereby futhermore creating said lower section of said conductive plugs;
• depositing a third layer of polysilicon over said surface;
• and
• patterning said third layer of polysilicon to from said upper of said conductive plug.

A method of forming a conductive plug in an opening provided for this purpose in a layer of dielectric said conductive plug forming the electrical interface between an overlying layer or contact point of interconnect metal said conductive plug having an upper section and lower section, comprising the steps of:

• depositing a layer of insulation over said layer of dielectric;
• patterning said layer of insulation, removing said layer of insulation from above said underlying layer or contact point of interconnect metal, creating openings in said layer of insulation that align with said underlying contact point of interconnect metal;
• blanket depositing a first layer of heavily doped polysilicon over the surface of said layer of insulation thereby including said openings in said dielectric;
• depositing a second layer of lightly doped polysilicon over said first layer;
• performing a Rapid Thermal Anneal to said first and said second layers;
• removing said second layer of lightly doped polysilicon thereby futhermore partially removing said first layer of heavily doped polysilicon to where the surface of said first layer of heavily doped polysilicon is equal to or below the surface of said layer of insulation thereby creating the lower section of said conductive plug, creating a plane of interface between said lower and said upper section of said conductive plug;
• depositing a third layer of lightly doped polysilicon over said plane of interface thereby including the surface of said layer of insulation;
• and
• patterning said third layer of lightly doped polysilicon to form said upper section of said conductive plug whereby said upper section of said conductive plug aligns with said lower section of said conductive plug.