Dual material gate MOSFET technique
AssigneeAdvanced Micro Devices, Inc.
InventorsQi Xiang, Joong Jeon
Life of this patent
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Abstract
This invention comprises a new technique to realize a dual material gate MOSFET. The inventive technique is base upon an asymmetric oxide spacer formation and a self-aligned silicide formation. The asymmetric oxide spacer on the sidewall of the drain side of the gate is formed by selectively etching the spacer on the source side. The etch selectivity is realized by nitrogen implantation into an oxide spacer on the source side, by utilizing preferably an angled ion implantation technique. An HF solution has been experimentally demonstrated to provide an etch rate of the nitrogen implanted oxide that is much faster than the oxide without the nitrogen implantation.
Claims42
A method of fabricating a plural material gate for a circuit device, comprising the steps of:
- a) providing a gate structure on a substrate, the gate structure having a top surface, and first and second sides,
- b) depositing a first layer on the gate structure, including a substantial portion of the top surface, and first and second sides,
- c) projecting a plurality of ions at a non-perpendicular angle, with respect to the top surface of the gate structure, wherein a first portion of the first layer adjacent to the first side of the gate structure, has a greater number of ions implanted than a second portion of the first layer adjacent to the second side of the gate structure,
- d) selectively etching the first layer so as to expose at least a portion of the first side of the gate structure while not exposing the second side,
- e) forming a silicide region in the first side of the gate structure, but not the second side of the gate structure, by utilizing the second portion of the first layer as a shield, and
- f) removing the second portion of the first layer.
A method of forming a dual-material gate for an FET comprising the steps of:
- a) providing a gate structure on a substrate, the gate having a first and second side,
- b) forming a barrier layer over the gate structure, a first portion of the barrier layer adjacent the first side, and a second portion of the barrier layer adjacent the second side,
- c) directing implant ions onto the gate structure and substrate at an angle so as to shield the second portion against the ions, thereby forming a relatively lower concentration of ions in the second portion than in the first portion, thereby comprising a different ion concentration relationship,
- d) removing the first portion while retaining the second portion in a selective etching process based upon the different ion concentration relationship,
- e) forming a silicide region in the first side of the gate structure by utilizing the second portion of the first layer as a shield,
- f) removing the second portion of the first layer.
A method of fabricating a plural material gate for a circuit device, comprising the steps of:
- a. providing a gate structure on a substrate, the gate structure having a top surface, and first and second sides,
- b. depositing a first layer on the gate structure, including a substantial portion of the top surface, and first and second sides,
- c. projecting a plurality of ions at a non-perpendicular angle, with respect to the top surface of the gate structure, wherein a second portion of the first layer adjacent to the second side of the gate structure, has a fewer number of ions implanted than a first portion of the first layer adjacent to the first side of the gate structure,
- d. processing the first layer to provide an asymmetric oxide spacer to shield at least a part of a second side of the gate structure,
- e. forming a silicide region on at least a part of a first side of the gate structure.
Dependencies are inferred from the claim text.