Method of manufacturing a gate structure for a semiconductor memory device with improved breakdown voltage and leakage rate

A method of manufacturing a semiconductor memory device comprising the steps of:

• a) forming a first insulating layer on a semiconductor substrate having one conductivity type;
• b) forming a first conductive layer on said first insulating layer;
• c) forming a first silicon dioxide sub-layer on said first conductive layer;
• d) forming a silicon nitride sub-layer on said first silicon dioxide sub-layer;
• e) Annealing said silicon nitride sub-layer in a nitrogen and oxygen containing gas;
• f) forming a second silicon dioxide sub-layer on said annealed silicon nitride sub-layer;
• g) forming a second conductive layer on said second silicon dioxide sub-layer;
• h) patterning said first insulating layer, said first conductive layer, said first silicon dioxide sub-layer, said annealed silicon nitride sub-layer, said second silicon dioxide sub-layer, and said second conductive layer to form a floating gate, an intergate dielectric layer, and a control gate;
• and
• i) forming a source and a drain.

A method of manufacturing a semiconductor memory device comprising the steps of:

• a) forming a first insulating layer on a semiconductor substrate having one conductivity type;
• b) forming a first conductive layer on said first insulating layer;
• c) forming a first silicon dioxide sublayer on said first conductive layer;
• d) forming a silicon nitride sub-layer on said first silicon dioxide sub-layer;
• e) forming a silicon oxynitride sub-layer by rapid thermal processing said silicon nitride layer in a nitrogen and oxygen containing gas at a temperature in the range between 900° C. and 1100° C.;
• at a pressure in the range between about 10 kPa and 100 kPa;
• for a period of time between 20 seconds and 180 seconds;
• f) forming a second silicon dioxide sub-layer on said silicon oxynitride sub-layer;
• g) forming a second conductive layer on said second silicon dioxide sub-layer;
• h) patterning said first insulating layer, said first conductive layer, said first silicon dioxide sub-layer, said annealed silicon nitride sublayer, said second silicon dioxide sub-layer, and said second conductive layer to form a floating gate, an intergate dielectric layer, and a control gate;
• and
• i) forming a source and a drain.

A method of manufacturing a semiconductor memory device comprising the steps of:

• a) forming a first insulating layer on a semiconductor substrate having one conductivity type;
• b) forming a first conductive layer on said first insulating layer;
• c) forming a second insulating layer by sequentially stacking:
• (i) a first silicon dioxide layer;
• (ii) a silicon nitride layer;
• (iii) a silicon oxynitride layer;
• and
• (iv) a second silicon dioxide layer;
• on said first conductive layer;
• d) forming a second conductive layer on said second insulating layer;
• and
• e) patterning said first insulating layer, said first conductive layer, said second insulating layer, and said second conductive layer to form a floating gate, an integrate dielectric layer, and a control gate;
• wherein said silicon oxynitride layer is formed by rapid thermal processing said silicon nitride layer in a nitrogen and oxygen containing gas.