Semiconductor structure having heterogeneous silicide regions and method for forming same

A semiconductor device fabrication process, comprising the steps of:

• forming a dielectric layer over a silicon substrate;
• forming a polysilicon layer over the dielectric layer;
• disposing a refractory metal into a first portion of the polysilicon layer;
• patterning the polysilicon layer and the dielectric layer to form a first gate outside the first portion of the polysilicon layer and a second gate within the first portion of the polysilicon layer;
• doping the silicon substrate to form a first source region and a first drain region adjacent the first gate, and a second source region and a second drain region adjacent the second gate;
• depositing a precursory metal on the polysilicon layer and on the silicon substrate;
• annealing the silicon substrate at a temperature between approximately 550 degrees Celsius and approximately 750 degrees Celsius;
• wherein the precursory metal on the polysilicon layer in the first gate interacts with silicon, forming a first silicide gate electrode of a first crystal phase;
• wherein the precursory metal on the silicon substrate overlying the first source region and the first drain region interacts with silicon, forming a first silicide source electrode and a first silicide drain electrode, respectively, of the first crystal phase over the first source region;
• and
• wherein the refractory metal lowers a crystal phase transforming barrier and induces the precursory metal on the polysilicon layer in the second gate to interact with silicon, forming a second silicide gate electrode of a second crystal phase.