Chip scale packages and methods for manufacturing the chip scale packages at wafer level

A method for manufacturing a semiconductor package, comprising:

• providing a semiconductor wafer having a plurality of semiconductor integrated circuit chips and a plurality of scribe lines, each of the semiconductor circuit chip having a plurality of chip pads and a passivation layer thereon;
• forming a patterned conductor layer directly on the passivation layer;
• forming an insulation layer on the patterned conductor layer;
• forming a plurality of external terminals of the semiconductor package, wherein the insulation layer includes a plurality of openings through which the external terminals connect to the patterned conductor layer, and the patterned conductor layer connects the chip pads to respective external terminals;
• forming a reinforcing layer on the insulation layer, wherein the external terminals are exposed through the reinforcing layer;
• and
• sawing the wafer to separate the semiconductor integrated circuit chips.

A method for manufacturing a semiconductor package, comprising:

• providing a semiconductor wafer having a plurality of semiconductor integrated circuit chips and a plurality of scribe lines, each of the semiconductor integrated circuit chips having a plurality of chip pads and a passivation layer thereon;
• forming a lower insulation layer on the passivation layer of the semiconductor chip, the lower insulation layer having openings over the chip pads;
• forming a patterned conductor layer which connects to the chip pads through the openings in the lower insulation layer;
• forming an upper insulation layer on the patterned conductor layer, the upper insulation layer having openings which expose portions of the patterned conductor layer;
• forming a plurality of external terminals of the semiconductor package at the openings in the upper insulation layer, the external terminals connecting to the patterned conductor layer, wherein the patterned conductor layer interconnects each of the chip pads to respective external terminals;
• forming a reinforcing layer on the upper insulation layer;
• and
• sawing the wafer to separate the semiconductor integrated circuit chips.