CMOS integrated circuit device and its inspecting method and device
AssigneeKabushiki Kaisha Toshiba
InventorTadahiro Kuroda
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Abstract
The disclosed device and method can inspect the CMOS integrated circuit devices at high precision on the basis of the static current of the voltage supply connected thereto. A CMOS integrated circuit comprises: at least one CMOS circuit having at least one P-channel MOS transistor and at least one N-channel MOS transistor; a first pad connected to a source of the P-channel MOS transistor; a second pad connected to a source of the N-channel MOS transistor; a third pad connected to an N-type substrate or an N-type well formed with the P-channel MOS transistor; and a fourth pad connected to a P-type substrate or a P-type well formed with the N-channel MOS transistor.
Claims2
The device for inspecting a CMOS integrated circuit device comprising at least one CMOS circuit having at least one P-channel MOS transistor and at least one N-channel MOS transistor;
- a first pad connected to a source of the P-channel MOS transistor;
- a second pad connected to a source of the N-channel MOS transistor;
- a third pad connected to an N-type substrate or an N-type well on which the P-channel MOS transistor is formed;
- and a fourth pad connected to a P-type substrate or a P-type well on which the N-channel MOS transistor is formed, said device comprises:
- first means for applying a first supply potential to the first pad, and a second supply potential lower than the first supply potential to the second pad;
- second means for applying a supply potential higher than the first supply potential to the third pad, and a supply potential lower than the second supply potential to the fourth pad;
- and
- third means for selectively rejecting the CMOS integrated circuit device on the basis of current flowing through the first or second pad.
The device for inspecting a CMOS integrated circuit device comprising at least one CMOS circuit having at least one P-channel MOS transistor and at least one N-channel MOS transistor;
- a first pad connected to a source of the P-channel MOS transistor;
- a second pad connected to a source of the N-channel MOS transistor;
- a third pad connected to an N-type substrate or an N-type well on which the P-channel MOS transistor is formed;
- and a fourth pad connected to a P-type substrate or a P-type well on which the N-channel transistor is formed, said device comprises:
- first means for applying a supply potential higher than first supply potential to the third pad, and a supply potential lower than the second supply potential to the fourth pad;
- and
- second means for applying a third supply potential lower than the first supply potential but higher than the second supply potential to the first pad, and a fourth supply potential lower than the third supply potential but higher than the second supply potential to the second pad, the second supply potential being lower than the first supply potential.
Dependencies are inferred from the claim text.