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US 6,185,731 B2Granted
Real time debugger for a microcomputer
AssigneesMitsubishi Electric Semiconductor Software Co., Ltd., Mitsubishi Denki Kabushiki Kaisha
InventorsShohei Maeda, Nobusuke Abe, Yoshikazu Satoh
Life of this patent
Estimating the term…
Abstract
The microcomputer provides with surroundings where data in a RAM can be monitored on the outside without employing an external bus. When a command requesting accessing to a RAM is received from an external monitor, a real time debugger built in the microcomputer confirms that a CPU is not accessing the RAM, and accesses the RAM. On the other hand, when accessing to an emROM, which emulates an actual ROM, is requested from the monitor, the real time debugger accesses one of emROMs which is not being used by the CPU at present.
Claims22
A microcomputer, comprising:
- a CPU for performing processing in accordance with a program;
- a RAM for storing data to be used by said CPU, said CPU switching itself, under its own control, to one of a first state characterized by suspension of access to the RAM and a second state characterized by access to the RAM;
- and
- a real time debugger for reading out, when a read address of said RAM is received from the outside, data in said RAM whenever said real time debugger detects that said CPU is in said first state and outputting the read out data to the outside, without placing said CPU in a hold state or causing said microcomputer to enter a special state reserved for debugging.
1 more element
A microcomputer, comprising:
- a CPU for performing processing in accordance with a program;
- a RAM for storing data to be used by said CPU, said CPU switching itself, under its own control, to one of a first state characterized by suspension of access to the RAM and a second state characterized by access to the RAM;
- a first internal bus that provides communication between the CPU and the RAM;
- a second internal bus, bypassing the CPU, that provides communication with the RAM;
- and
- a real time debugger for reading out, when a read address of said RAM is received from outside the microcomputer, data in said RAM via the second internal bus at a time when said real time debugger detects that said CPU is in said first state and outputting the read out data outside the microcomputer, without placing said CPU in a hold state or causing said microcomputer to enter a special state reserved for debugging.
3 more elements
A microcomputer, comprising:
- a CPU for performing processing in accordance with a program;
- a RAM for storing data to be used by said CPU, said CPU switching itself, under its own control, to one of a first state characterized by suspension of access to the RAM and a second state characterized by access to the RAM;
- and
- a real time debugger for reading out, when a read address of said RAM is received from outside the microcomputer, data in said RAM at a time when said real time debugger detects that said CPU is in said first state by using a switch that selectively provides one of the CPU and the real time debugger access to said RAM, and outputting the read out data outside the microcomputer, without placing said CPU in a hold state or causing said microcomputer to enter a special state reserved for debugging.
1 more element
A microcomputer, comprising:
- a CPU for performing processing in accordance with a program;
- a RAM for storing data to be used by said CPU;
- and
- a real time debugger for reading out, when a read address of said RAM is received from the outside, data in said RAM whenever said CPU does not access said RAM and outputting the read out data to the outside,
- wherein said real time debugger writes data into said RAM in response to a request from the outside when said CPU is not accessing said RAM, and said real time debugger includes a control section for receiving a command including command data designating an operation condition of said real time debugger and address data designating a read address and performing an operation in accordance with the received command.
2 more elements
A microcomputer, comprising:
- a CPU for performing processing in accordance with a program;
- a RAM for storing data to be used by said CPU;
- and
- a real time debugger for reading out, when a read address of said RAM is received from the outside, data in said RAM whenever said CPU does not access said RAM and outputting the read out data to the outside,
- wherein said real time debugger writes data into said RAM in response to a request from the outside when said CPU is not accessing said RAM, and said real time debugger outputs, upon starting of sending out of data to be outputted to the outside, a signal having a pulse width corresponding to a command by which the data are requested.
2 more elements
Dependencies are inferred from the claim text.