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US 6,185,726 B2Granted
System and method for efficiently designing integrated circuit devices
AssigneesSony Corporation, Sony Electronics Inc.
InventorChen-Chi Chou
Life of this patent
Estimating the term…
Abstract
A system and method for efficiently designing integrated circuits provides a verification manager for verifying an integrated circuit design, a synthesis manager for synthesizing the integrated circuit design, a backend manager for implementing the integrated circuit design, and a processor for simultaneously controlling the verification manager, the synthesis manager, and the backend manager to create the integrated circuit design. The system and method generates a series of regression checkpoints controlled by the verification manager, and a series of timing checkpoints controlled by the synthesis manager to facilitate and expedite the integrated circuit design procedure.
Claims26
A system for creating an electrical circuit design, comprising:
- a verification manager configured to verify said electrical circuit design, wherein said verification manager corrects at least one electrical circuit design defect, generates new design code as a result of the correction, simulates operation of said electrical circuit design, and performs a plurality of regression tests on said electrical circuit design, wherein said plurality of regression tests are comprised of a plurality of regression checkpoints that check a regression log for an error indication, update a design defect report, update a test vector matrix, check whether at least one source code is stored in a memory, and check whether a regression test was passed;
- a synthesis manager configured to synthesize said electrical circuit design, wherein said synthesis manager performs a synthesis procedure on said electrical circuit design, performs at least one timing test, modifies at least one constraint script when said electrical circuit design fails a timing test, and generates a first net list for said electrical circuit design, wherein said at least one timing test is comprised of a plurality of timing checkpoints that check whether at least one source code and at least one script are stored in a memory, check a timing log and at least one warning indicator for at least one error indication, check said electrical circuit design for unconnected points, check timing for said electrical circuit design, check at least one fanout parameter for said electrical circuit design, and check at least one clock timing, at least one reset buffer, and at least one fanout buffer;
- a backend manager configured to implement said electrical circuit design, wherein said backend manager creates a layout for said electrical circuit design, generates a second net list, generates an estimated standard delay format annotated to said second net list, generates an actual standard delay format, and performs a final regression test utilizing said actual standard delay format;
- and
- a processor, coupled to said system, to control said verification manager, said synthesis manager, and said backend manager and create said electrical circuit design.
2 more elements
A method for creating an electrical circuit design, comprising the steps of:
- verifying said electrical circuit design using a verification manager, wherein said verification manager performs the steps of correcting at least one electrical circuit design defect, generating new design code as a result of the correction, simulating operation of said electrical circuit design, and performing a plurality of regression tests on said electrical circuit design, wherein said plurality of regression tests are comprised of a plurality of regression checkpoints that perform the steps of checking a regression log for an error indication, updating a design defect report, updating a test vector matrix, checking whether at least one source code is stored in a memory, and checking whether a regression test was passed;
- synthesizing said electrical circuit design using a synthesis manager, wherein said synthesis manager performs the steps of performing at least one timing test, modifying at least one constraint script when said electrical circuit design fails a timing test, and generating a first net list for said electrical circuit design, wherein said at least one timing test is comprised of a plurality of timing checkpoints that perform the steps of checking whether at least one source code and at least one script are stored in a memory, checking a timing log and at least one warning indicator for at least one error indication, checking said electrical circuit design for unconnected points, checking timing for said electrical circuit design, checking at least one fanout parameter for said electrical circuit design, and checking at least one clock timing, at least one reset buffer, and at least one fanout buffer;
- implementing said electrical circuit design using a backend manager, wherein said backend manager performs the steps of creating a layout for said electrical circuit design, generating a second net list, generating an estimated standard delay format annotated to said second net list, generating an actual standard delay format, and performing a final regression test utilizing said actual standard delay format;
- and
- controlling said verification manager, said synthesis manager, and said backend manager with a processor to thereby create said electrical circuit design.
2 more elements
A computer-readable medium comprising program instructions for creating an electrical circuit design by performing the steps of:
- verifying said electrical circuit design using a verification manager, wherein said verification manager performs the steps of correcting at least one electrical circuit design defect, generating new design code as a result of the correction, simulating operation of said electrical circuit design, and performing a plurality of regression tests on said electrical circuit design, wherein said plurality of regression tests are comprised of a plurality of regression checkpoints that perform the steps of checking a regression log for an error indication, updating a design defect report, updating a test vector matrix, checking whether at least one source code is stored in a memory, and checking whether a regression test was passed;
- synthesizing said electrical circuit design using a synthesis manager, wherein said synthesis manager performs the steps of performing at least one timing test, modifying at least one constraint script when said electrical circuit design fails a timing test, and generating a first net list for said electrical circuit design, wherein said at least one timing test is comprised of a plurality of timing checkpoints that perform the steps of checking whether at least one source code and at least one script are stored in a memory, checking a timing log and at least one warning indicator for at least one error indication, checking said electrical circuit design for unconnected points, checking timing for said electrical circuit design, checking at least one fanout parameter for said electrical circuit design, and checking at least one clock timing, at least one reset buffer, and at least one fanout buffer;
- implementing said electrical circuit design using a backend manager, wherein said backend manager performs the steps of creating a layout for said electrical circuit design, generating a second net list, generating an estimated standard delay format annotated to said second net list, generating an actual standard delay format, and performing a final regression test utilizing said actual standard delay format;
- and
- controlling said verification manager, said synthesis manager, and said backend manager with a processor to thereby create said electrical circuit design.
2 more elements
A system for creating an electrical circuit design, comprising:
- means for verifying said electrical circuit design using a verification manager, wherein said means for verifying is comprised of means for correcting at least one electrical circuit design defect, means for generating new design code as a result of the correction, means for simulating operation of said electrical circuit design, and means for performing a plurality of regression tests on said electrical circuit design, wherein said plurality of regression tests are comprised of a plurality of regression checkpoints comprising means for checking a regression log for an error indication, means for updating a design defect report, means for updating a test vector matrix, means for checking whether at least one source code is stored in a memory, and means for checking whether a regression test was passed;
- means for synthesizing said electrical circuit design, wherein said means for synthesizing is comprised of means for performing at least one timing test, means for modifying at least one constraint script when said electrical circuit design fails a timing test, and means for generating a first net list for said electrical circuit design, wherein said at least one timing test is comprised of a plurality of timing checkpoints comprised of means for checking whether at least one source code and at least one script are stored in a memory, means for checking a timing log and at least one warning indicator for at least one error indication, means for checking said electrical circuit design for unconnected points, means for checking timing for said electrical circuit design, means for checking at least one fanout parameter for said electrical circuit design, and means for checking at least one clock timing, at least one reset buffer, and at least one fanout buffer;
- means for implementing said electrical circuit design, wherein said means for implementing is comprised of means for creating a layout for said electrical circuit design, means for generating a second net list, means for generating an estimated standard delay format annotated to said second net list, means for generating an actual standard delay format, and means for performing a final regression test utilizing said actual standard delay format;
- and
- means for controlling said means for verifying, said means for synthesizing, and said means for implementing to thereby create said electrical circuit design.
2 more elements
Dependencies are inferred from the claim text.