Apparatus and method for partitioning logic into a programmable logic device
AssigneeAltera Corporation
InventorBruce Pedersen
Life of this patent
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Abstract
A method of partitioning logic into a programmable logic device includes the steps of synthesizing a logic design into a network of hierarchical components. Each hierarchical component is then mapped to a minimum number of logic array blocks in a programmable logic device. The mapping operation may be performed by independently synthesizing the hierarchical components into a network of virtual logic elements, assigning the virtual logic elements to virtual logic array blocks, and mapping the virtual logic array blocks to the logic array blocks in the programmable logic device.
Claims7
A method of partitioning a logic design into a programmable logic device, said method comprising the steps of:
- forming a network of hierarchical components for implementation within physical logic array blocks of a programmable logic device;
- synthesizing said hierarchical components into a network of virtual logic elements;
- assigning said virtual logic elements to virtual logic array blocks;
- and
- mapping said virtual logic array blocks to said physical logic array blocks of said programmable logic device.
A computer readable memory to direct a computer to function in a specified manner, comprising:
- executable instructions to form a network of hierarchical components for implementation within physical logic array blocks of a programmable logic device;
- executable instructions to synthesize said hierarchical components into a network of virtual logic elements;
- executable instructions to assign said virtual logic elements to virtual logic array blocks;
- and
- executable instructions to map said virtual logic array blocks to said physical logic array blocks of said programmable logic device.
Dependencies are inferred from the claim text.