Method for performing timing analysis of a clock-shaping circuit
AssigneeInternational Business Machines Corporation
InventorsTimothy Michael Burks, Robert Edward Mains
Life of this patent
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Abstract
A methodology is implemented for accurately and precisely computing the output signal times for clock circuit in a data processing system (600) using transistor-level static timing analysis tools which compute delays of blocks or subcircuits that correspond to channel-connected components of transistors. During execution of the Static timing analysis, the predictability of clock signals is recognized and denoted in a timing model (616-622). Furthermore, an actual logical function of the clock circuit is determined during execution of the static timing analysis to provide more precise knowledge of the rise and fall times of the signals provided to the clock circuit.
Claims27
A method for performing a timing analysis of a clock circuit, comprising the steps of:
- receiving a plurality of input signals at a node of the clock circuit;
- determining a phase corresponding to a first one of the plurality of input signals of the node;
- and
- generating a simulation pattern which enables an output of the node to transition from a first logic state to a second logic state by applying a generated signal which has the phase corresponding to the first one of the plurality of input signals of the node.
A method for performing static timing analysis of a circuit, comprising the steps of:
- generating a timer model from the circuit;
- generating a phase table using the timer model;
- determining a plurality of arrival time assertions using the phase table and the timer model, wherein the plurality of arrival time assertions indicate a plurality of actual signal event times and a plurality of phases associated with an event;
- propagating the plurality of phases through the model of the circuit to identify each of a plurality of nodes of the circuit as one of a clock node and a data node;
- and
- computing a delay and an arrival time for each of the plurality of nodes in the circuit, wherein the step of computing comprises the steps of:
- receiving a plurality of input signals of a first one of the plurality of nodes;
- determining a phase corresponding to a first one of the plurality of input signals of the first one of the plurality of nodes;
- and
- generating a simulation pattern which enables an output of the first one of the plurality of nodes to transition from a first logic state to a second logic state by applying a generated signal which has the phase corresponding to the first one of the plurality of input signals of the first one of the plurality of nodes.
A data processing system, comprising:
- a memory for storing a model of a clock circuit;
- and
- a data processor for computing a delay between a first signal being provided to a node of the clock circuit and a second signal being output by the node of the clock circuit in response to the first signal, the data processor computing the delay by determining a phase corresponding to the first signal and applying a generated signal which has the phase corresponding to the first signal to the node.
A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for performing a timing analysis of a clock circuit, said method steps comprising:
- receiving a plurality of input signals at a node of the clock circuit;
- determining a phase corresponding to a first one of the plurality of input signals of the node;
- and
- generating a simulation pattern which enables an output of the node to transition from a first logic state to a second logic state by applying a generated signal which has the phase corresponding to the first one of the plurality of input signals of the node.
Dependencies are inferred from the claim text.