Method of design for testability at RTL and integrated circuit designed by the same

A method of design for testability at a register transfer level comprising:

• a partitioning step for partitioning an RTL circuit, which is an integrated circuit designed at the register transfer level, into blocks each satisfying a previously defined simply testable condition,
• wherein said simply testable condition is that a circuit in each of said blocks has an acyclic structure including no feedback loop and said circuit has a sequential depth not exceeding a predetermined value.

A method of design for testability at a register transfer level comprising:

• a partitioning step for partitioning an RTL circuit, which is an integrated circuit designed at the register transfer level, into blocks each satisfying a previously defined simply testable condition,
• wherein said simply testable condition is that a circuit in each of said blocks has an n-fold line-up structure in which signal paths between an arbitrary register and an arbitrary external output or pseudo-external output have n sorts or less of sequential depths, wherein n is a positive integer.

A method of design for testability at a register transfer level comprising:

• a partitioning step for partitioning an RTL circuit, which is an integrated circuit designed at the register transfer level, into blocks each satisfying a previously defined simply testable condition,
• wherein said simply testable condition is that a circuit in each of said blocks has a line-up structure in which each register belongs to merely one time frame obtained through time-axis expansion about an arbitrary external output or pseudo-external output.

A method of design for testability at a register transfer level comprising:

• a partitioning step for partitioning an RTL circuit, which is an integrated circuit designed at the register transfer level, into blocks each satisfying a previously defined simply testable condition,
• wherein said simply testable condition is that a circuit in each of said blocks has a line-up structure in which each register belongs to merely one time frame obtained through time-axis expansion about an arbitrary external output or pseudo-external output and said circuit has a sequential depth not exceeding a predetermined value.

A method of design for testability at a register transfer level comprising:

• a partitioning step for partitioning an RTL circuit, which is an integrated circuit designed at the register transfer level, into blocks each satisfying a previously defined simply testable condition,
• wherein said simply testable condition is that a circuit in each of said blocks has an acyclic structure including no feedback loop and said circuit has a sequential depth not exceeding a predetermined value and that a circuit in each of said blocks has a combinational test pattern generation complexity.

A method of design for testability at a register transfer level comprising:

• a partitioning step for partitioning an RTL circuit, which is an integrated circuit designed at the register transfer level, into blocks each satisfying a previously defined simply testable condition, wherein said simply testable condition is that a circuit in each of said blocks has an acyclic structure including no feedback loop and said circuit has a sequential depth not exceeding a predetermined value,
• said partitioning step includes a process for obtaining relationship on Teachableness between each input and each output of said block by extracting an input reachable to each output, and obtaining a plurality of inputs of said block whose value is controllable through a common external input pin of said RTL circuit on the basis of said relationship.

A method of design for testability at a register transfer level comprising:

• a partitioning step for partitioning an RTL circuit, which is an integrated circuit designed at the register transfer level, into blocks each satisfying a previously defined simply testable condition, wherein said simply testable condition is that a circuit in each of said blocks has an acyclic structure including no feedback loop and said circuit has a sequential depth not exceeding a predetermined value,
• said partitioning step includes, when any functional facilities has a larger input number or larger output number than said RTL circuit, a process for converting said functional facility into an equivalent circuit including functional facilities each having a smaller input number and a smaller output number than said RTL circuit.

A method of design for testability at a register transfer level comprising:

• a partitioning step for partitioning an RTL circuit, which is an integrated circuit designed at the register transfer level, into blocks each satisfying a previously defined simply testable condition, wherein said simply testable condition is that a circuit in each of said blocks has an acyclic structure including no feedback loop and said circuit has a sequential depth not exceeding a predetermined value,
• wherein said partitioning step includes a process for collecting finite state machines included in said RTL circuit in a common block.

An integrated circuit, which is partitioned into plural blocks through test simplifying design at a register transfer level and adapted such that a circuit in each of said blocks has an acyclic structure including no feedback loop and said circuit has a sequential depth not exceeding a predetermined value,

• wherein a plurality of inputs of one block are commonly connected with one external input pin of said integrated circuit.

An integrated circuit, which is partitioned into plural blocks through test simplifying design at a register transfer level and adapted such that a circuit in each of said blocks has an acyclic structure including no feedback loop and said circuit has a sequential depth not exceeding a predetermined value,

• wherein each of said blocks includes a scan chain for making an input signal controllable and an output signal observable from the outside of said integrated circuit.