Slaveless synchronous system design
AssigneeIntel Corporation
InventorJashojiban Banik
Life of this patent
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Abstract
An apparatus includes a master latch of a master/slave flip-flop, wherein the master latch includes a first data output. The apparatus also includes a logic coupled to receive the first data output, wherein the logic includes a second data output without using a slave latch of a master/slave flip-flop, and a non-slave latch coupled to receive the second data output.
Claims18
A method comprising:
- checking whether a propagation delay of a data path that includes a master/slave flip-flop is longer than a particular time duration;
- and
- if the propagation delay of the data path is longer than the particular time duration, then removing a slave latch of the master/slave flip-flop from the data path by routing output data from a master latch of the master/slave flip-flop to a pulse latch.
An apparatus comprising:
- timing control logic to check whether a propagation delay of a data path is longer than a particular time duration;
- and
- modification logic, coupled to the timing control logic, to reconfigure the data path by removing a slave latch of a master/slave flip-flop from the data path if the propagation delay of the data path is longer than the particular time duration and route output data from a master latch of the master/slave flip-flop to a pulse latch.
A method comprising:
- identifying a data path in a hardware design that includes a master/slave flip-flop, the master/slave flip-flop having a master latch and a slave latch;
- and
- reconfiguring the data path by removing at least the slave latch and combining logic, if any, on either side of the slave latch.
A machine-readable medium having stored thereon data representing sequences of instruction which, when executed on a general purpose machine, perform slaveless synchronous system design by:
- checking whether a propagation delay of a data path that includes a master/slave flip-flop is longer than a particular time duration;
- and
- if the propagation delay of the data path is longer than the particular time duration, then removing a slave latch of the master/slave flip-flop from the data path by routing output data from a master latch of the master/slave flip-flop to a pulse latch.
A machine-readable medium having stored thereon data representing sequences of instructions which, when executed by a general purpose machine, perform slaveless synchronous system design by:
- identifying a data path in a hardware design that includes a master/slave flip-flop, the master/slave flip-flop having a master latch and a slave latch;
- and
- reconfiguring the data path by removing at least the slave latch and combining logic, if any, on either side of the slave latch.
Dependencies are inferred from the claim text.