Memory card design with parity and ECC for non-parity and non-ECC systems
AssigneeInternational Business Machines Corporation
InventorsTimothy J. Dell, Kamal E. Dimitri, Kent A. Dramstad, Marc R. Faucher, Bruce G. Hazelzet, Bruce W. Singer
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Abstract
A memory card design which adds parity for non-parity computer systems to supply error detection capabilities is provided. The apparatus includes a memory card, parity DRAM locatable on the memory card, logic for generating and checking parity bits and logic for the control of the generating, checking and storing parity bits. Also, in another embodiment, the apparatus adds error correction code to the memory card to provide error detection and correction code to systems lacking such capabilities.
Claims26
A memory card apparatus for adding parity to a non-parity computer system, the memory card apparatus comprising:
- a) a memory card;
- b) a parity RAM, locatable on said memory card;
- c) logic for generating, checking and storing parity bits in said parity RAM;
- d) logic for controlling said logic for generating and checking parity bits;
- and
- e) an error indicator and logic for controlling and decoding said error indicator.
A memory card apparatus for adding parity to a non-parity computer system, the memory card apparatus comprising:
- a) a memory card;
- b) a parity RAM locatable on said memory card;
- c) logic for generating, checking and storing parity bits in said RAM;
- d) logic for controlling the generating, checking and storing of parity bits in said parity RAM;
- e) first and second error indicators;
- and
- f) logic for controlling and decoding said error indicators.
A memory card apparatus for adding error correction code to a non-error correction code and non-parity system;
- a) a memory card;
- b) an ECC RAM locatable on said memory card;
- c) logic for generating and checking ECC in communication with said ECC RAM;
- d) logic for correcting errors in communication with said logic for generating, checking and storing ECC in said RAM;
- e) an error indicator in communication with said logic for checking ECC;
- and
- f) logic for controlling said error indicator.
Dependencies are inferred from the claim text.