Chip performance optimization with self programmed built in self test

A Dynamic Random Access Memory (DRAM), comprising:

• a DRAM core;
• Self Programmable Built In Self Test (SPBIST) logic connected to test said DRAM core, said SPBIST testing said DRAM core to determine an optimum performance parameter of said DRAM core;
• control logic providing control parameters for controlling operation of said DRAM core;
• and
• a non-volatile storage for storing the optimum performance parameter of said DRAM core as determined by said SPBIST, said non-volatile storage automatically providing the optimum performance parameter to said control logic during a subsequent power up of said circuit, said control logic controlling said DRAM core so that said DRAM core operates based on the optimum performance parameter.

An integrated circuit chip comprising:

• a circuit core;
• Built In Self Test (BIST) logic connected to test and control said circuit core during a test condition;
• control logic providing control parameters to said circuit core responsive to said BIST logic during said test condition;
• and
• non-volatile storage receiving control information from said BIST logic during said test condition and providing control information to said control logic during a normal power up.

A method for tuning an integrated circuit chip for optimum performance, comprising:

• testing a circuit on the chip to determine an optimum performance parameter of the circuit;
• storing the optimum performance parameter in a memory on the chip;
• supplying power to the chip:
• and
• setting the circuit to operate based on the optimum performance parameter stored in said memory, said setting step being automatically performed in response to said power supplying step.

A method for controlling operation of a DRAM, comprising:

• testing a sense amplifier circuit of the DRAM to determine an optimum delay time for setting the sense amplifier;
• storing the optimum delay time in a memory on the chip;
• supplying power to the chip:
• and
• setting the sense amplifier circuit to operate based on the optimum delay time stored in said memory, said setting step being automatically performed in response to said power supplying step.