Methods and apparatus for synchronizing asynchronous test structures and eliminating clock skew considerations
AssigneeSun Microsystems, Inc.
InventorsArthur T. Leung, Dale Greenley
Life of this patent
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Abstract
A synchronizing circuit receives an external signal and yields an output that is synchronized with the system clock and operates at the frequency of the external signal. The signal output from the synchronizing circuit is fed into the clock-enable input of the storage element, and the system clock signal is fed into the clock input of the storage element. Because the clock-enable signal triggers the storage element, the storage element is driven at the external signal frequency. Clock skew is eliminated because the system clock used for the clock input to the storage element is skew-controlled.
Claims22
A method of driving a storage element based on unsynchronized external signals that are not skew-controlled, in an environment having a synchronized, skew-controlled system clock signal, comprising:
- receiving an external clock-enable signal;
- synchronizing the external clock-enable signal with the system clock signal to create a synchronized CE signal;
- transmitting the synchronized CE signal to a clock-enable input of the storage element;
- and
- receiving the system clock signal at a clock input of the storage element.
A method of driving an edge-triggered flip flop based on JTAG signals that are not skew-controlled, in an environment having a synchronized, skew-controlled system clock signal, comprising:
- receiving a JTAG clock-enable signal;
- synchronizing the JTAG CE signal with the system clock signal to create a JTAG CE signal that is synchronized to the system clock signal;
- transmitting the synchronized JTAG CE signal to a clock-enable input of the flip flop;
- and
- receiving the system clock signal at a clock input of the flip flop.
A method for using JTAG signals to access data noninvasively from an edge-triggered primary storage element that operates in an integrated circuit having a synchronized, skew-controlled system clock signal, comprising:
- receiving an output of the primary storage element as an input to a secondary storage element;
- receiving a JTAG CE signal;
- synchronizing the JTAG CE signal with the system clock signal to create a synchronized JTAG CE signal;
- transmitting the synchronized JTAG CE signal to a clock-enable input of the secondary storage element;
- and
- receiving the system clock signal at a clock input of the secondary storage element.
An apparatus for driving a storage element based on unsynchronized external signals that are not skew-controlled, in an environment having a synchronized, skew-controlled system clock signal, comprising:
- means for receiving an external clock-enable signal;
- means for synchronizing the external clock-enable signal with the system clock signal to create a synchronized CE signal;
- means for transmitting the synchronized CE signal to a clock-enable input of the storage element;
- and
- means for receiving the system clock signal at a clock input of the storage element.
An apparatus for driving an edge-triggered flip flop based on JTAG signals that are not skew-controlled, in an environment having a synchronized, skew-controlled system clock signal, comprising:
- means for receiving a JTAG clock-enable signal;
- means for synchronizing the JTAG CE signal with the system clock signal to create a JTAG CE signal that is synchronized to the system clock signal;
- means for transmitting the synchronized JTAG CE signal to a clock-enable input of the flip flop;
- and
- means for receiving the system clock signal at a clock input of the flip flop.
An apparatus for using JTAG signals to access data noninvasively from an edge-triggered primary storage element that operates in an integrated circuit having a synchronized, skew-controlled system clock signal, comprising:
- means for receiving an output of the primary storage element as an input to a secondary storage element;
- means for receiving a JTAG CE signal;
- means for synchronizing the JTAG CE signal with the system clock signal to create a synchronized JTAG CE signal;
- means for transmitting the synchronized JTAG CE signal to a clock-enable input of the secondary storage element;
- and
- means for receiving the system clock signal at a clock input of the secondary storage element.
An apparatus for driving an edge-triggered storage element based on unsynchronized external signals that are not skew-controlled, in an environment having a synchronized, skew-controlled system clock signal, comprising:
- a first synchronizing circuit having a first input connected to an external clock-enable signal, a second input connected to the system clock signal, and an output;
- and
- an edge-triggered storage element having a clock-enable input connected to the output of the first synchronizing circuit, a clock input connected to the system clock signal, and an output.
An apparatus for using unsynchronized external signals that are not skew-controlled to drive a storage element operating in an environment having a synchronized, skew-controlled system clock signal, comprising:
- a synchronizing circuit having a first input connected to an external clock-enable signal, a second input connected to the system clock signal, and an output;
- a logic AND element having a first input connected to the output of the synchronizing circuit, a second input connected to the system clock signal, and an output;
- and
- a storage element having a clock input connected to the output of the logic AND element.
A system for driving an edge-triggered secondary storage element based on unsynchronized external signals that are not skew-controlled, in an environment having a synchronized, skew-controlled system clock signal, comprising:
- a primary storage element that stores data and has an output;
- an edge-triggered secondary storage element having an input connected to the output of the primary storage element, a clock input connected to the system clock, and a clock-enable input;
- and
- a synchronizing circuit having a first input connected to an external clock-enable signal, a second input connected to the system clock signal, and an output connected to the clock-enable input of the edge-triggered secondary storage element.
Dependencies are inferred from the claim text.