High-performance IEEE1149.1-compliant boundary scan cell

An integrated circuit, comprising:

• a substrate;
• an integrated circuit formed within said substrate, said integrated circuit including:
• a latch circuit including a slave latch and a master latch having a data output, said slave latch including at least a first data input connected to said data output of said master latch, a second data input, and a control input that receives a control signal that controls latching of data present at said second data input by said slave latch;
• and
• boundary scan cell circuitry connected to said second data input and to said control input, wherein said boundary scan cell circuitry supplies said control signal and said data to said slave latch;
• functional logic coupled to said latch circuit.

An apparatus, comprising:

• a circuit card;
• and
• an integrated circuit mounted on said circuit card, said integrated circuit including:
• a latch circuit including a slave latch and a master latch having a data output, said slave latch including at least a first data input connected to said data output of said master latch, a second data input, and a control input that receives a control signal that controls latching of data present at said second data input by said slave latch;
• and
• boundary scan cell circuitry connected to said second data input and to said control input, wherein said boundary scan cell circuitry supplies said control signal and said data to said slave latch.