US 6,185,706 B2 · Performance monitoring circuitry for integrated circuits

Abstract

Process monitoring circuitry according to the invention incorporates test structures placed across an integrated circuit die to monitor the performance of the fabrication process across the die. The integrity of the semiconductor fabrication process used to manufacture a particular integrated circuit is ascertained by comparing data extracted the test structures by automated test equipment (ATE) to simulation values. In one embodiment in the invention, the process monitoring circuitry comprises inverters arranged in a generally linear fashion. The inverters may be composed of simple CMOS inverters or other logic gates configured as inverters. The logic gates are arranged in horizontal and/or vertical test paths in which the gates are disposed across various sections of the integrated circuit die. An input test pad and an output test pad for each test path are provided at opposing sides of the integrated circuit die. In one alternate embodiment of the invention, multiplexing circuitry is utilized at the input and output test pads in order to minimize the impact of the process monitoring circuitry. The various test paths may incorporate comparatively lengthy metal routing lines, allowing accurate measurement of metal interconnect delays.

Claims21

Dependent claims

Process monitor circuitry for an integrated circuit having a core logic region and a plurality of bond pads, the integrated circuit manufactured in a semiconductor process having at least first and second types of transistors for forming logic gates, the process monitor circuitry comprising:

an input bond pad;
an output bond pad, the input and output bond pads disposed on opposing sides of the integrated circuit;
and
a plurality of logic gates disposed in the core logic region and coupled in series between the input bond pad and the output bond pad to form a first test path, the first test path providing output pulses at the output bond pad in response to input pulses at the input bond pad, the output pulses including information representative of the relative electrical characteristics of the first type of transistor and the second type of transistor.

1 more element

A method for monitoring a semiconductor manufacturing process having at least first and second types of transistors for forming logic gates, the semiconductor process further utilizing multiple layers of interconnect material to form interconnect wires for signal paths between circuit components, the method comprising the steps of:

providing an integrated circuit having a core logic portion and a plurality of bond pads, the integrated circuit further having process monitor circuitry, the process monitor circuitry comprising an input bond pad and an output bond pad, the input and output bond pads disposed on opposing sides of the core logic region, and a plurality of logic gates disposed in the core logic region and coupled in series between the input bond pad and the output bond pad to form a test path, the test path providing output pulses at the output bond pad in response to input pulses at the input bond pad, the output pulses including information representative of the relative electrical characteristics of the first type of transistor and the second type of transistor;
applying a test pattern to the input bond pad of the process monitor circuitry;
recording the resulting output pulses of the process monitor circuitry;
and
comparing the output pulses of the process monitor circuitry to predetermined test values reflecting acceptable process variations.

2 more elements

Dependencies are inferred from the claim text.

Performance monitoring circuitry for integrated circuits

Life of this patent

Performance monitoring circuitry for integrated circuits

Life of this patent

Abstract

Claims21