Disk-array controller
AssigneeNEC Corporation
InventorKazuya Shiraishi
Life of this patent
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Abstract
A disk-array controller of the present invention has data-buffers 70-75 accessible from a host device and disk units, various selectors 42-69, XOR circuits 78-79, parity check circuits 76-77. By changing the settings of these components, transmission passes are changed. The settings can be programmed more than one by set registers 340-394 and execution counters 34-39. Using time-sharing buses such as PCI buses 15, 18, each program performs parallel processing because plural programs time-share the transmission bus during the period of acquiring access permission to the bus.
Claims9
A disk-array controller, comprising:
- data buffers accessible from any of a host device and disk units;
- exclusive-OR circuits for carrying out exclusive-OR operations;
- circuits for checking redundant parity, where outputs of the exclusive-OR circuits are determined as true when the outputs are all zero “0”;
- selectors for selecting outputs from the host devices or the disk units and outputs from the exclusive-OR circuits and transferring selected outputs to the data buffers;
- selectors for selecting whether or not to transport outputs from each of the data buffers to the exclusive-OR circuits;
- selectors for selecting whether or not to transport outputs from the host device or the disk units;
- selectors for selecting whether or not to transport all one “1” to the exclusive-OR circuits to reverse outputs of the exclusive-OR circuit;
- and
- transfer buses for transferring outputs of the exclusive-OR circuits to the host device and the disk units,
- wherein
- the transfer buses are determined by adjusting a selection of the selectors at the time of transmission.
A disk-array controller having a host device and a plurality of disk units, comprising:
- a first bus connecting to the host device;
- a second bus connecting to a plurality of the disk units;
- a plurality of data buffers connecting between the first bus and the second bus through input selectors and output selectors;
- a first exclusive-OR circuit in which output of the output selector, output of the first bus, and output of a selector which outputs odd or even are provided as inputs;
- a second exclusive-OR circuit in which output of the output selector, output of the second bus, and output of a selector which outputs odd or even are provided as inputs;
- and
- a control unit for controlling the selections of the input selectors and the output selectors, wherein
- outputs of the first exclusive-OR circuit and the second exclusive-OR circuit are stored in any of a plurality of the data buffers.
Dependencies are inferred from the claim text.