US 6,185,694 B2 · Dynamic clock distribution

Abstract

A system including a first graphics controller and an expansion slot for coupling a second graphics controller. The first graphics controller generates first graphic symbols based on data stored in the system memory in synchronism with clock signals received from a clock circuit. Similarly, the second graphics controller generates second graphic symbols based on data stored in the system memory in synchronism with clock signals received from the clock circuit. When the second graphics controller is not coupled to the expansion slot, the processor provides a graphics select signal. A clock steering circuit responds to the graphics select signal by applying the clock signals to the first graphics controller, while blocking the clock signals to the expansion slot. In the absence of the graphics select signal, the clock steering circuit applies the clock signals to the expansion slot for application to the second graphics controller, while blocking the clock signals to the first graphics controller.

Claims15

Dependent claims

A clock control circuit, comprising:

a source of a select signal for selecting between operation of a first functional block and a second functional block;
a clock steering circuit for receiving clock signals from a clock signal source and responsive to a first predetermined state of the select signal for preventing received clock signals from being applied to the first functional block while enabling received clock signals to be applied to the second functional block, said clock steering circuit being responsive to a second predetermined state of the select signal for enabling received clock signals to be applied to the first functional block while preventing received clock signals from being applied to the second functional block.

A graphics clock control circuit, comprising:

a source of a graphics select signal;
and
a clock steering circuit for receiving clock signals from a clock signal source and responsive to a first predetermined state of the graphics select signal for preventing received clock signals from being applied to a first graphics controller connection while enabling received clock signals to be applied to a second graphics controller connection, said clock steering circuit being responsive to a second predetermined state of the graphics select signal for enabling received clock signals to be applied to said first graphics controller connection while preventing received clock signals from being applied to said second graphics controller connection.

A method of selecting one of a first graphics controller and an expansion slot for receipt of clock signals, said method comprising:

(a) detecting whether a second graphics controller is coupled to the expansion slot;
(b) when the second graphics controller is coupled to the expansion slot, causing a graphics select signal to have a first predetermined state;
(c) when the second graphics controller is not coupled to the expansion slot, causing the graphics select signal to have a second predetermined state;
(d) when the graphics select signal is in a first one of the first predetermined state and the second predetermined state, applying the clock signals to the first graphics controller and blocking the clock signals to the expansion slot;
and
(e) when the graphics select signal is in an opposite one of the first predetermined state and the second predetermined state, applying the clock signals to the expansion slot for application to the second graphics controller and blocking the clock signals to the first graphics controller.

3 more elements

Dependencies are inferred from the claim text.

Dynamic clock distribution

Life of this patent

Dynamic clock distribution

Life of this patent

Abstract

Claims15