US 6,185,693 B2Granted

Synchronous interface for transmitting data in a system of massively parallel processors

AssigneeInternational Business Machines Corporation

InventorsDerrick Leroy Garmire, Robert Stanley Capowski, Daniel Francis Casper, Christine Marie Desnoyers, Frank David Ferraiolo, Marten Jan Halma, Robert Frederick Stucke

Life of this patent

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Abstract

A massively parallel system has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal. Digital data is transmitted at high speeds via the parallel bus to provide a scalable communications network for parallel processing systems while eliminating precise bus length and system clock rates as a critical or limiting factor.

Claims3

Dependent claims

A method for semi-synchronous transmission of data among a plurality of processors, each of said plurality of processors having a local processor clock, said method including the steps of:

transmitting data bytes from a transmitting processor to a receiving processor in parallel with respective bits of each byte coupled to a separate line of a parallel bus, said bits coupled to each said separate line in response to a transmit clock signal;
transmitting said transmit clock signal from said transmitting processor to said receiving processor on a separate line of said parallel bus;
phase aligning separately, at said receiving processor, each bit on each separate line with said transmit clock signal that has been transmitted to said receiver in the previously recited step of transmitting said transmit clock signal;
synchronizing said local processor clock of said receiving processor with said transmit clock signal.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 08/669,667Filed 24 Jun 1996 · continuation
Priority: 17 Jun 1994
Granted: 6 Feb 2001
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 15/17375
Non hierarchical topologies: one dimensional, e.g. linear array, ring
G06F 13/4256
On a daisy chain bus: using a clocked protocol
G06F 15/17
Interprocessor communication: using an input/output type connection, e.g. channel, I/O port
G06F
Computing and data processing