Clock generation
AssigneeIntel Corporation
InventorsJayanti L. Gandhi, Chao Zhang
Life of this patent
Estimating the term…
Abstract
A clock divider receives a main clock and generates divided clocks (even or odd division) each having generally a half duty cycle. The clock divider includes flip flops connected to form a master-slave counter in which the master components are clocked off a first clock and the slave components are clocked off a second clock that is inverted from the first clock. The master-slave counter is a ring counter, and outputs from the master-slave counter are routed to decoding circuitry to generate divided clocks.
Claims29
A clocking circuit for generating an output clock, comprising:
- a master counting device coupled to receive a first clock;
- a slave counting device coupled to receive a second clock, the second clock being an inverted version of the first clock;
- and
- a decoder receiving outputs of the master and slave counting devices to generate an output clock that is a divided version of the first clock.
A clock divider for dividing a main clock, comprising:
- a master-slave ring counter having a master portion clocked by the main clock and a slave portion clocked by an inverted version of the main clock;
- and
- a decoder receiving outputs of the ring counter to generate a divided clock.
An electronic device, comprising:
- a main clock generator;
- and
- a clock divider connected to receive the main clock and generate an output clock that is divided from the main clock by a predetermined number, the clock divider including a counter having master and slave portions, the master portion clocked by the main clock and the slave portion clocked by an inverted version of the main clock.
A method of generating a divided clock from a main clock and an inverted version of the main clock, the method comprising:
- advancing a master counter in response to the main clock;
- advancing a slave counter in response to an inverted version of the main clock;
- and
- decoding output bits from the master and slave counters to generate the divided clock.
A computer system, comprising:
- a processor;
- a bus device;
- a master clock generator;
- and
- a clock divider receiving the master clock to generate a first clock to the processor and a second clock to the bus device,
- wherein the first and second clocks are divided from the master clock, and at least one of the first and second clocks is divided by an odd number, the odd number divided clock having generally a half duty cycle.
Dependencies are inferred from the claim text.