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AssigneeIntel Corporation
InventorsMitchell Alexander Poplingher, Carl Scafidi, Tse-Yu Yeh, Wenliang Chen
Estimating the term…
A pipelined microprocessor having a branch prediction unit implemented in an instruction pointer generation stage of the microprocessor. The branch prediction unit includes a memory device having at least a first entry configured to hold at least a part of a memory address of a pre-selected branch instruction and at least a part of a memory address of a branch target corresponding to the pre-selected branch instruction. The branch prediction unit compares an instruction pointer of an instruction to be executed with the memory address of the pre-selected branch instruction. In response to a match between the instruction pointer and the memory address of pre-selected branch instruction, the unit causes the microprocessor to fetch an instruction corresponding to the branch target. In one embodiment, the instruction pointer generation stage of the microprocessor is implemented as a first stage of the pipelined microprocessor. In addition, the branch prediction unit is compares the instruction pointer and the memory address of the pre-selected branch instruction during a single clock cycle in which the instruction pointer is generated.
A pipelined microprocessor comprising a branch prediction unit to operate in conjunction with an instruction pointer generation stage of said microprocessor, said microprocessor having a fetch stage separate and subsequent from said instruction pointer generation stage, said branch prediction unit to perform branch prediction on a first instruction in parallel with said instruction pointer generation stage generating an instruction pointer for a second instruction, said second instruction being sequential to said first instruction in a program sequence.
A pipelined microprocessor comprising:
A method for predicting branch instructions implemented in a pipelined microprocessor, said method comprising:
Dependencies are inferred from the claim text.